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-- $Id: pdp11_sequencer.vhd 556 2014-05-29 19:01:39Z mueller $
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-- $Id: pdp11_sequencer.vhd 569 2014-07-13 14:36:32Z mueller $
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--
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--
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-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Description: pdp11: CPU sequencer
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-- Description: pdp11: CPU sequencer
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--
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--
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-- Dependencies: ib_sel
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-- Dependencies: ib_sel
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.31
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit;
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-- use DP_STAT.div_quit; set munit_s_div_sr;
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-- BUGFIX: s_opg_div_sr: check for late div_quit
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-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
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-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
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-- 2011-11-18 427 1.4.2 now numeric_std clean
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-- 2011-11-18 427 1.4.2 now numeric_std clean
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-- 2010-10-23 335 1.4.1 use ib_sel
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-- 2010-10-23 335 1.4.1 use ib_sel
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-- 2010-10-17 333 1.4 use ibus V2 interface
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-- 2010-10-17 333 1.4 use ibus V2 interface
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-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
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-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
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s_opg_div,
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s_opg_div,
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s_opg_div_cn,
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s_opg_div_cn,
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s_opg_div_cr,
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s_opg_div_cr,
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s_opg_div_sq,
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s_opg_div_sq,
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s_opg_div_sr,
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s_opg_div_sr,
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s_opg_div_zero,
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s_opg_div_quit,
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s_opg_ash,
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s_opg_ash,
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s_opg_ash_cn,
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s_opg_ash_cn,
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s_opg_ashc,
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s_opg_ashc,
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s_opg_ashc_cn,
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s_opg_ashc_cn,
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s_opg_ashc_wl,
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s_opg_ashc_wl,
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ndpcntl.munit_s_div_cn := '1';
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ndpcntl.munit_s_div_cn := '1';
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
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ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
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ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
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ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
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nstate := s_opg_div_cn;
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nstate := s_opg_div_cn;
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if DP_STAT.div_zero='1' or DP_STAT.div_ovfl='1' then
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if DP_STAT.div_quit = '1' then
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nstate := s_opg_div_zero;
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nstate := s_opg_div_quit;
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else
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else
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ndpcntl.dsrc_we := '1'; -- update DSRC
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ndpcntl.dsrc_we := '1'; -- update DSRC
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ndpcntl.dtmp_we := '1'; -- update DTMP
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ndpcntl.dtmp_we := '1'; -- update DTMP
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end if;
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end if;
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if DP_STAT.shc_tc = '1' then
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if DP_STAT.shc_tc = '1' then
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nstate := s_opg_div_cr;
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nstate := s_opg_div_cr;
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end if;
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end if;
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when s_opg_div_cr => -- DIV (reminder correction)
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when s_opg_div_cr => -- DIV (remainder correction)
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ndpcntl.munit_s_div_cr := '1';
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ndpcntl.munit_s_div_cr := '1';
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
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ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
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ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
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ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
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nstate := s_opg_div_sq;
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nstate := s_opg_div_sq;
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when s_opg_div_sq => -- DIV (store quotient)
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when s_opg_div_sq => -- DIV (correct and store quotient)
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ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
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ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
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ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
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ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
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ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
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ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
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ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
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ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
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ndpcntl.gpr_adst := SRCREG; -- write result
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ndpcntl.gpr_adst := SRCREG; -- write result
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ndpcntl.gpr_we := '1';
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ndpcntl.gpr_we := '1';
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ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
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ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
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ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
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ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
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nstate := s_opg_div_sr;
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nstate := s_opg_div_sr;
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when s_opg_div_sr => -- DIV (store reminder)
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when s_opg_div_sr => -- DIV (store remainder)
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ndpcntl.munit_s_div_sr := '1';
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ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
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ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
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ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
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ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
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ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
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ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
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ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
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ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
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ndpcntl.gpr_we := '1';
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ndpcntl.gpr_we := '1';
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ndpcntl.psr_ccwe := '1';
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ndpcntl.psr_ccwe := '1';
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if DP_STAT.div_quit = '1' then
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nstate := s_opg_div_quit;
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else
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do_fork_next(nstate, nstatus, nmmumoni);
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do_fork_next(nstate, nstatus, nmmumoni);
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end if;
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when s_opg_div_zero => -- DIV (/0 or 0/ abort)
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when s_opg_div_quit => -- DIV (0/ or /0 or V=1 aborts)
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ndpcntl.psr_ccwe := '1';
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ndpcntl.psr_ccwe := '1';
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do_fork_next(nstate, nstatus, nmmumoni);
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do_fork_next(nstate, nstatus, nmmumoni);
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when s_opg_ash => -- ASH (load shc)
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when s_opg_ash => -- ASH (load shc)
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ndpcntl.munit_s_ash := '1';
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ndpcntl.munit_s_ash := '1';
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