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-- $Id: pdp11_ubmap.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_ubmap.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: pdp11_ubmap - syn
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-- Module Name: pdp11_ubmap - syn
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-- Description: pdp11: 11/70 unibus mapper
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-- Description: pdp11: 11/70 unibus mapper
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--
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--
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-- Dependencies: -
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-- Dependencies: memlib/ram_1swar_gen
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-- ib_sel
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.1.1 use ib_sel
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-- 2010-10-17 333 1.1 use ibus V2 interface
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-- 2008-08-22 161 1.0.1 use iblib
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-- 2008-08-22 161 1.0.1 use iblib
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-- 2008-01-27 115 1.0 Initial version
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-- 2008-01-27 115 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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architecture syn of pdp11_ubmap is
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architecture syn of pdp11_ubmap is
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constant ibaddr_ubmap : slv16 := conv_std_logic_vector(8#170200#,16);
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constant ibaddr_ubmap : slv16 := conv_std_logic_vector(8#170200#,16);
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signal IBSEL_UBMAP : slbit := '0';
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signal MAP_2_WE : slbit := '0';
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signal MAP_2_WE : slbit := '0';
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signal MAP_1_WE : slbit := '0';
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signal MAP_1_WE : slbit := '0';
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signal MAP_0_WE : slbit := '0';
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signal MAP_0_WE : slbit := '0';
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signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
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signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
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signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
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signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
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WE => MAP_0_WE,
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WE => MAP_0_WE,
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ADDR => MAP_ADDR,
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ADDR => MAP_ADDR,
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DI => IB_MREQ.din(7 downto 1),
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DI => IB_MREQ.din(7 downto 1),
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DO => MAP_DOUT(7 downto 1));
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DO => MAP_DOUT(7 downto 1));
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proc_comb: process (MREQ, ADDR_UB, IB_MREQ, MAP_DOUT)
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SEL : ib_sel
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variable ibsel : slbit := '0';
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generic map (
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IB_ADDR => ibaddr_ubmap,
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SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
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port map (
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CLK => CLK,
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IB_MREQ => IB_MREQ,
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SEL => IBSEL_UBMAP
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);
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proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
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variable ibusy : slbit := '0';
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variable ibusy : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable iwe2 : slbit := '0';
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variable iwe2 : slbit := '0';
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variable iwe1 : slbit := '0';
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variable iwe1 : slbit := '0';
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variable iwe0 : slbit := '0';
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variable iwe0 : slbit := '0';
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variable iaddr : slv5 := (others=>'0');
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variable iaddr : slv5 := (others=>'0');
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begin
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begin
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ibsel := '0';
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ibusy := '0';
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ibusy := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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iwe2 := '0';
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iwe2 := '0';
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iwe1 := '0';
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iwe1 := '0';
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iwe0 := '0';
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iwe0 := '0';
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iaddr := (others=>'0');
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iaddr := (others=>'0');
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if IB_MREQ.req = '1' and
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if IBSEL_UBMAP = '1' then
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IB_MREQ.addr(12 downto 7)=ibaddr_ubmap(12 downto 7) then
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ibsel := '1';
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end if;
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if ibsel = '1' then
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if IB_MREQ.addr(1) = '1' then
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if IB_MREQ.addr(1) = '1' then
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idout(5 downto 0) := MAP_DOUT(21 downto 16);
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idout(5 downto 0) := MAP_DOUT(21 downto 16);
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else
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else
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idout(15 downto 1) := MAP_DOUT(15 downto 1);
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idout(15 downto 1) := MAP_DOUT(15 downto 1);
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end if;
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end if;
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if MREQ = '1' then -- if map request, stall ib cycle
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if MREQ = '1' then -- if map request, stall ib cycle
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ibusy := '1';
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ibusy := '1';
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end if;
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end if;
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end if;
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end if;
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if ibsel='1' and IB_MREQ.we='1' then
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if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
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if IB_MREQ.addr(1)='1' then
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if IB_MREQ.addr(1)='1' then
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if IB_MREQ.be0 = '1' then
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if IB_MREQ.be0 = '1' then
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iwe2 := '1';
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iwe2 := '1';
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end if;
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end if;
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else
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else
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MAP_1_WE <= iwe1;
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MAP_1_WE <= iwe1;
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MAP_0_WE <= iwe0;
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MAP_0_WE <= iwe0;
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ADDR_PM <= unsigned(MAP_DOUT) + unsigned("000000000"&ADDR_UB(12 downto 1));
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ADDR_PM <= unsigned(MAP_DOUT) + unsigned("000000000"&ADDR_UB(12 downto 1));
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IB_SRES.ack <= ibsel;
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IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
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IB_SRES.busy <= ibusy;
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IB_SRES.busy <= ibusy;
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IB_SRES.dout <= idout;
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IB_SRES.dout <= idout;
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end process proc_comb;
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end process proc_comb;
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