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-- $Id: tb_pdp11core.vhd 352 2011-01-02 13:01:37Z mueller $
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-- $Id: tb_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 - 0.26 - - c:ok
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-- 2007-10-07 88 - 0.26 - - c:ok
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.3.2 now numeric_std clean
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
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-- 2007-09-02 79 1.0 Initial version
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-- 2007-09-02 79 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.simlib.all;
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xmicmd := "wmi";
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xmicmd := "wmi";
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next file_loop;
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next file_loop;
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when "rr| " => -- rr[0-7]
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when "rr| " => -- rr[0-7]
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ifunc := c_cpfunc_rreg;
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ifunc := c_cpfunc_rreg;
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irnum := conv_std_logic_vector(rind, 3);
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irnum := slv(to_unsigned(rind, 3));
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readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
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readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
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when "wr| " => -- wr[0-7]
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when "wr| " => -- wr[0-7]
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ifunc := c_cpfunc_wreg;
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ifunc := c_cpfunc_wreg;
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irnum := conv_std_logic_vector(rind, 3);
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irnum := slv(to_unsigned(rind, 3));
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readoct_ea(iline, idin);
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readoct_ea(iline, idin);
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-- Note: there are no field definitions for wal, wah, wibrb because
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-- Note: there are no field definitions for wal, wah, wibrb because
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-- there is no corresponding cp command. Therefore the
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-- there is no corresponding cp command. Therefore the
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-- rbus field definitions are used here
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-- rbus field definitions are used here
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dcycle := dcycle + 1;
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dcycle := dcycle + 1;
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idelta := idelta - 1;
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idelta := idelta - 1;
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end loop;
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end loop;
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if imemi then -- rmi or wmi seen ? then inc ar
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if imemi then -- rmi or wmi seen ? then inc ar
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r_addr := unsigned(r_addr) + 1;
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r_addr := slv(unsigned(r_addr) + 1);
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end if;
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end if;
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write(oline, dcycle, right, 4);
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write(oline, dcycle, right, 4);
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write(oline, string'(" "));
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write(oline, string'(" "));
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if ireq then
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if ireq then
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proc_moni: process
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proc_moni: process
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begin
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begin
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loop
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loop
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wait until CLK'event and CLK='1';
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wait until rising_edge(CLK);
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wait for c2out_time;
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wait for c2out_time;
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R_WAITOK <= '0';
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R_WAITOK <= '0';
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if R_WAITCMD = '1' then
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if R_WAITCMD = '1' then
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if CP_STAT_cmdack = '1' then
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if CP_STAT_cmdack = '1' then
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