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# $Id: INSTALL.txt 433 2011-11-27 22:04:39Z mueller $
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# $Id: INSTALL.txt 467 2013-01-02 19:49:05Z mueller $
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Guide to install and build w11a systems, test benches and support software
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Guide to install and build w11a systems, test benches and support software
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Table of content:
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Table of content:
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1. Download
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1. Download
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2. Setup environment variables
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2. System requirements
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3. Compile UNISIM/SIMPRIM libraries for ghdl
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3. Setup system environment
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4. Compile and install the support software
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a. Setup environment variables
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b. Setup USB access
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4. Compile UNISIM/SIMPRIM libraries for ghdl
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5. Compile and install the support software
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a. Compile sharable libraries
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a. Compile sharable libraries
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b. Setup Tcl packages
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b. Setup Tcl packages
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5. The build system
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c. Rebuild Cypress FX2 firmware
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6. Building test benches
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6. The build system
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7. Building test benches
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a. General instructions
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a. General instructions
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b. Available test benches
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b. Available test benches
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7. Building systems
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8. Building systems
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a. General instructions
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a. General instructions
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b. Available systems
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b. Configuring FPGAs
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c. Available systems
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1. Download ---------------------------------------------------------------
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1. Download ---------------------------------------------------------------
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All instructions below assume that the project files reside in a
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All instructions below assume that the project files reside in a
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working directory with the name represented as
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working directory with the name represented as
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To download latest snapshot of trunk
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To download latest snapshot of trunk
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cd
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cd
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svn co http://opencores.org/ocsvn/w11/w11/trunk
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svn co http://opencores.org/ocsvn/w11/w11/trunk
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2. Setup environment variables --------------------------------------------
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2. System requirements ----------------------------------------------------
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This project contains not only VHDL code but also support software. Therefore
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quite a few software packages are expected to be installed. The following
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list gives the Ubuntu/Debian package names, but mapping this to other
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distributions should be straight forward.
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- building the bit files for the FPGAs requires a Xilinx WebPACK installation
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- building and using the RLink backend software requires:
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- full C/C++ development chain (gcc,g++,cpp,make)
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-> package: build-essential
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- Boost C++ library (>= 1.40), with date-time, thread, and regex
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-> package: libboost-dev libboost-date-time-dev libboost-thread-dev
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libboost-regex-dev
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- libusb 1.0 (>= 1.0.6)
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-> package: libusb-1.0-0-dev
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- Perl (>= 5.10) (usually included in base installations)
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- Tcl (>= 8.4), with tclreadline support
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-> package: tcl tcl-dev tcllib tclreadline
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- the download contains pre-build firmware images for the Cypress FX2
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USB Interface. Re-building them requires
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- Small Device C Compiler
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-> package: sdcc sdcc-ucsim
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- for FX2 firmware download and jtag programming over USB one needs
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- fxload
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-> package: fxload
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- urjtag
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-> package: urjtag for Ubuntu 12.04
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-> see INSTALL_urjtag.txt for other distributions !!
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- for VHDL simulations one needs
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- ghdl
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-> see INSTALL_ghdl.txt for the unfortunately gory details
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- optional but very useful is:
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- gtkwave
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-> package: gtkwave
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3. Setup system environment -----------------------------------------------
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3a. Setup environment variables --------------------------------------
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The make flow for building test benches (ghdl and ISim based) and systems
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The make flow for building test benches (ghdl and ISim based) and systems
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(Xilinx xst based) as well as the support software (mainly the rlink backend
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(Xilinx xst based) as well as the support software (mainly the rlink backend
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server) requires
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server) requires
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- the definition of the environment variables:
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- the definition of the environment variables:
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- RETROBASE: must refer to the installation root directory
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- RETROBASE: must refer to the installation root directory
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- BOOSTINC: pathname for includes of boost library
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- BOOSTINC: pathname for includes of boost library
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- TCLINC: pathname for includes of Tcl runtime library
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- RETRO_FX2_VID and RETRO_FX2_PID: default USB VID/PID, see below
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- that the tools binary directory is in the path
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- that the tools binary directory is in the path
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- that the tools library directory is in the library path
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- that the tools library directory is in the library path
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For bash and alike use
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For bash and alike use
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export RETROBASE=
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export RETROBASE=
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export PATH=$PATH:$RETROBASE/tools/bin
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export PATH=$PATH:$RETROBASE/tools/bin
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export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
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export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
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In most cases the boost library version coming with the distribution will
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In most cases the boost library version coming with the distribution will
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work, in those cases simply use
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work, similar for Tcl, in those cases simply use
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export BOOSTINC=/usr/include
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export BOOSTINC=/usr/include
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export TCLINC=/usr/include/tcl8.5
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After that building functional model based test benches will work. If you
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After that building functional model based test benches will work. If you
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want to also build post-xst or post-par test benches read next section.
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want to also build post-xst or post-par test benches read next section.
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3. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
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If the Cypress USB controller available on Digilent Nexys2, Nexys3 and
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Atlys boards is used the default USB VID and PID is defined by two
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environment variables. For internal lab use one can use
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export RETRO_FX2_VID=16c0
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export RETRO_FX2_PID=03ef
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!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
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!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
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!! misuse of the defaults provided with the project sources. !!
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!! Usage of this VID/PID in any commercial product is forbidden. !!
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3b. Setup USB access -------------------------------------------------
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For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
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Atlys boards 'udev' rules must be setup to allow user level access to
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these devices. A set of rules is provided under
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$RETROBASE/tools/fx2/sys
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Follow the 'README.txt' file in this directory.
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Notes:
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- the provided udev rules use the VID/PID for 'internal lab use' as
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described above. If other VID/PID used the file must be modified.
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- your user account must be in group 'plugdev' (should be the default).
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4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
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The build system for test benches also supports test benches run against
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The build system for test benches also supports test benches run against
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the gate level models derived after the xst, map or par step. In this
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the gate level models derived after the xst, map or par step. In this
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case ghdl has to link against a compiled UNISIM or SIMPRIM library.
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case ghdl has to link against a compiled UNISIM or SIMPRIM library.
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xilinx_ghdl_unisim
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xilinx_ghdl_unisim
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xilinx_ghdl_simprim
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xilinx_ghdl_simprim
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If you have several WebPack versions installed, repeat for each version.
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If you have several WebPack versions installed, repeat for each version.
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4. Compile and install the support software -------------------------------
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5. Compile and install the support software -------------------------------
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4a. Compile sharable libraries ---------------------------------------
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5a. Compile sharable libraries ---------------------------------------
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Required tools and libraries:
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Required tools and libraries:
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g++ >= 4.3 (decltype support assumed in usage of boost::bind)
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g++ >= 4.3 (decltype support assumed in usage of boost::bind)
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boost >= 1.35 (boost::thread api changed, new one is used)
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boost >= 1.35 (boost::thread api changed, new one is used)
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linusb >= 1.0.5 (timerfd support)
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Build was tested under:
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Build was tested under:
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ubuntu lucid (10.04 LTS): gcc 4.4.3 boost 1.40.0
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ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9
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debian lenny (5.0.8): gcc 4.3.2 boost 1.xx.x (t.b.c.)
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debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8
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To build all sharable libraries
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To build all sharable libraries
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cd $RETROBASE/tools/src
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cd $RETROBASE/tools/src
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make -j 4
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make -j 4
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cd $RETROBASE/tools/src
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cd $RETROBASE/tools/src
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rm_dep
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rm_dep
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make realclean
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make realclean
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4b. Setup Tcl environment --------------------------------------------
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5b. Setup Tcl environment --------------------------------------------
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The Tcl files are organized in several packages. To create the Tcl
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The Tcl files are organized in several packages. To create the Tcl
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package files (pkgIndex.tcl)
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package files (pkgIndex.tcl)
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cd $RETROBASE/tools/tcl
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cd $RETROBASE/tools/tcl
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cd $HOME
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cd $HOME
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ln -s $RETROBASE/tools/tcl/.tclshrc .
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ln -s $RETROBASE/tools/tcl/.tclshrc .
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ln -s $RETROBASE/tools/tcl/.wishrc .
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ln -s $RETROBASE/tools/tcl/.wishrc .
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5c. Rebuild Cypress FX2 firmware -------------------------------------
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The download includes pre-build firmware images for the Cypress FX2
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USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
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These firmware images are under
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$RETROBASE/tools/fx2/bin
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To re-build them, e.g. because a different USB VID/PID is to be used
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cd $RETROBASE/tools/fx2/src
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make clean
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make
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make install
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Please read README_USB_VID-PID.txt carefully to understand the usage
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of USB VID and PID.
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5. The build system -------------------------------------------------------
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6. The build system -------------------------------------------------------
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Simulation and synthesis tools usually need a list of the VHDL source
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Simulation and synthesis tools usually need a list of the VHDL source
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files, often in proper compilation order (libraries before components).
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files, often in proper compilation order (libraries before components).
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The different tools have different formats of these 'project files'.
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The different tools have different formats of these 'project files'.
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A full w11a is build from more than 80 source files, test benches from
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A full w11a is build from more than 80 source files, test benches from
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even more. Using the vbom's a large number of designs can be easily
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even more. Using the vbom's a large number of designs can be easily
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maintained.
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maintained.
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6. Building test benches --------------------------------------------------
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7. Building test benches --------------------------------------------------
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6a. General instructions ---------------------------------------------
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7a. General instructions ---------------------------------------------
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To compile a test bench named all is needed is
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To compile a test bench named all is needed is
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make
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make
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make _tsim # for post-par
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make _tsim # for post-par
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The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
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The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
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the compilation remains of earlier functional model compiles.
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the compilation remains of earlier functional model compiles.
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6b. Available test benches -------------------------------------------
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7b. Available test benches -------------------------------------------
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See file w11a_tb_guide.txt
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See file w11a_tb_guide.txt
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7. Building systems -------------------------------------------------------
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8. Building systems -------------------------------------------------------
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7a. General instructions ---------------------------------------------
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8a. General instructions ---------------------------------------------
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To generate a bit file for a system named all is needed is
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To generate a bit file for a system named all is needed is
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make .bit
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make .bit
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If only the xst or par output is wanted just use
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If only the xst or par output is wanted just use
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make .ngc
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make .ngc
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make .ncd
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make .ncd
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7b. Available systems ------------------------------------------------
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A simple 'message filter' system is also integrated into the make build flow.
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For many (though not all) systems a .mfset file has been provided which
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defines the xst,par and bitgen messages which are considered ok. To see
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only the remaining message extracted from the vaious .log files simply
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use the make target
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make .mfsum
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after a re-build.
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8b. Configuring FPGAs ------------------------------------------------
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The make flow supports also loading the bitstream into FPGAs, either
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via Xilinx Impact, or via the Cypress FX2 USB controller is available.
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For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
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simply use
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make .iconfig
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For using the Cypress FX2 USB controlle on Digilent Nexys2, Nexys3 and
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Atlys boards just connect the USB cable and
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make .jconfig
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This will automatically check and optionaly re-load the FX2 firmware
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to a version matching the FPGA design, generate a .svf file from the
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.bit file, and configure the FPGA. In case the bit file is out-of-date
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the whole design will be re-implemented before.
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8c. Available systems ------------------------------------------------
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Note: Currently ready to build versions exist for
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Note: Currently ready to build versions exist for
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Digilent S3BOARD (-1000 FPGA version)
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Digilent S3BOARD (-1000 FPGA version)
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Digilent Nexys2 board (-1200 FPGA version)
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Digilent Nexys2 board (-1200 FPGA version)
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Digilent Nexys3 board
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Digilent Nexys3 board
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b. for Digilent Nexys3 board
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b. for Digilent Nexys3 board
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
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make sys_tst_rlink_n3.bit
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make sys_tst_rlink_n3.bit
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2. w11a systems
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2. rlink over USB tester
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a. for Digilent Nexys2 board
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cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
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make sys_tst_rlink_cuff_ic_n2.bit
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3. w11a systems
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a. for Digilent S3BOARD
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a. for Digilent S3BOARD
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cd $RETROBASE/rtl/sys_gen/w11a/s3board
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cd $RETROBASE/rtl/sys_gen/w11a/s3board
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make sys_w11a_s3.bit
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make sys_w11a_s3.bit
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