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# $Id: INSTALL.txt 604 2014-11-16 22:33:09Z mueller $
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# $Id: INSTALL.txt 654 2015-03-01 18:45:38Z mueller $
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Guide to install and build w11a systems, test benches and support software
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Guide to install and build w11a systems, test benches and support software
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Table of content:
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Table of content:
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1. Download
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1. Download
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2. System requirements
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2. System requirements
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3. Setup system environment
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3. Setup environment variables
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a. Setup environment variables
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b. Setup USB access
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4. Compile UNISIM/SIMPRIM libraries for ghdl
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4. Compile UNISIM/SIMPRIM libraries for ghdl
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5. Compile and install the support software
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5. Compile and install the support software
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a. Compile sharable libraries
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a. Compile sharable libraries
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b. Setup Tcl packages
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b. Setup Tcl packages
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c. Rebuild Cypress FX2 firmware
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6. The build system
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6. The build system
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6 a. Setting up Xilinx environment with xtwi
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7. Building test benches
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7. Building test benches
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a. General instructions
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b. Available test benches
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8. Building systems
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8. Building systems
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a. General instructions
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b. Configuring FPGAs (via make flow)
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c. Configuring FPGAs (directly via config_wrapper)
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d. Available systems
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d. Available systems
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e. Available bitkits with bit and log files
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e. Available bitkits with bit and log files
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9. Generate Doxygen based source code view
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9. Generate Doxygen based source code view
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1. Download ---------------------------------------------------------------
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1. Download ---------------------------------------------------------------
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and download
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and download
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cd
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cd
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svn co -r http://opencores.org/ocsvn/w11/w11/trunk
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svn co -r http://opencores.org/ocsvn/w11/w11/trunk
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2. System requirements ----------------------------------------------------
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2. System requirements ----------------------------------------------------
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This project contains not only VHDL code but also support software. Therefore
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This project contains not only VHDL code but also support software. Therefore
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quite a few software packages are expected to be installed. The following
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quite a few software packages are expected to be installed. The following
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list gives the Ubuntu/Debian package names, but mapping this to other
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list gives the Ubuntu/Debian package names, but mapping this to other
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distributions should be straight forward.
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distributions should be straight forward.
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- building the bit files for the FPGAs requires a Xilinx WebPACK installation
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- building the bit files requires a Xilinx ISE WebPACK installation
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- building and using the RLink backend software requires:
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- building and using the RLink backend software requires:
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- full C/C++ development chain (gcc,g++,cpp,make)
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- full C/C++ development chain (gcc,g++,cpp,make)
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-> package: build-essential
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-> package: build-essential
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- Boost C++ library (>= 1.40), with date-time, thread, and regex
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- Boost C++ library (>= 1.40), with date-time, thread, and regex
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-> package: libboost-dev libboost-date-time-dev libboost-thread-dev
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-> package: libboost-dev libboost-date-time-dev libboost-thread-dev
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libboost-regex-dev
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libboost-regex-dev
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- libusb 1.0 (>= 1.0.6)
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- libusb 1.0 (>= 1.0.6)
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-> package: libusb-1.0-0-dev
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-> package: libusb-1.0-0-dev
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- Perl (>= 5.10) (usually included in base installations)
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- Perl (>= 5.10) (usually included in base installations)
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- Tcl (>= 8.4), with tclreadline support
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- Tcl (>= 8.5), with tclreadline support
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-> package: tcl tcl-dev tcllib tclreadline
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-> package: tcl tcl-dev tcllib tclreadline
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- the download contains pre-build firmware images for the Cypress FX2
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USB Interface. Re-building them requires
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- Small Device C Compiler
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-> package: sdcc sdcc-ucsim
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- for FX2 firmware download and jtag programming over USB one needs
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- fxload
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-> package: fxload
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- urjtag
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-> package: urjtag for Ubuntu 12.04
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-> see INSTALL_urjtag.txt for other distributions !!
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- for VHDL simulations one needs
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- for VHDL simulations one needs
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- ghdl
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- ghdl
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-> see INSTALL_ghdl.txt for the unfortunately gory details
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-> see INSTALL_ghdl.txt for the unfortunately gory details
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- additional requirements for using Cypress FX (on Nexys2/3) see
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INSTALL_fx2_support.txt
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- for doxygen documentation an up-to-date installation of doxygen is
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- for doxygen documentation an up-to-date installation of doxygen is
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required, version 1.8.3.1 or later
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required, version 1.8.3.1 or later
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- optional but very useful is:
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- optional but very useful is:
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- gtkwave
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- gtkwave
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-> package: gtkwave
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-> package: gtkwave
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3. Setup system environment -----------------------------------------------
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3. Setup environment variables --------------------------------------------
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3a. Setup environment variables --------------------------------------
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The make flow for building test benches (ghdl and ISim based) and systems
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The make flow for building test benches (ghdl and ISim based) and systems
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(Xilinx xst based) as well as the support software (mainly the rlink backend
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(Xilinx ISE xst based) as well as the support software (mainly the rlink
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server) requires
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backend server) requires
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- the definition of the environment variables:
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- the definition of the environment variables:
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- RETROBASE: must refer to the installation root directory
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- RETROBASE: must refer to the installation root directory
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- TCLINC: pathname for includes of Tcl runtime library
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- TCLINC: pathname for includes of Tcl runtime library
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- TCLLIBNAME: name of Tcl runtime library
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- TCLLIBNAME: name of Tcl runtime library
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and don't setup BOOSTINC and BOOSTLIB.
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and don't setup BOOSTINC and BOOSTLIB.
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After that building functional model based test benches will work. If you
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After that building functional model based test benches will work. If you
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want to also build post-xst or post-par test benches read next section.
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want to also build post-xst or post-par test benches read next section.
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If the Cypress USB controller available on Digilent Nexys2, Nexys3 and
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For Cypress FX2 (on Nexys2/3) related setup see INSTALL_fx2_support.txt
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Atlys boards is used the default USB VID and PID is defined by two
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environment variables. For internal lab use one can use
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export RETRO_FX2_VID=16c0
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export RETRO_FX2_PID=03ef
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!! Carefully read the disclaimer about usage of USB VID/PID numbers !!
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!! in the file README_USB-VID-PID.txt. You'll be responsible for any !!
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!! misuse of the defaults provided with the project sources. !!
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!! Usage of this VID/PID in any commercial product is forbidden. !!
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3b. Setup USB access -------------------------------------------------
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For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
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Atlys boards 'udev' rules must be setup to allow user level access to
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these devices. A set of rules is provided under
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$RETROBASE/tools/fx2/sys
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Follow the 'README.txt' file in this directory.
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Notes:
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- the provided udev rules use the VID/PID for 'internal lab use' as
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described above. If other VID/PID used the file must be modified.
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- your user account must be in group 'plugdev' (should be the default).
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4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
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4. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
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The build system for test benches also supports test benches run against
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The build system for test benches also supports test benches run against
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the gate level models derived after the xst, map or par step. In this
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the gate level models derived after the xst, map or par step. In this
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case ghdl has to link against a compiled UNISIM or SIMPRIM library.
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case ghdl has to link against a compiled UNISIM or SIMPRIM library.
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To make handling of the parallel installion of several WebPack versions
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To make handling of the parallel installion of several ISE WebPack versions
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easy the compiled libraries are stored in sub-directories under $XILINX:
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easy the compiled libraries are stored in sub-directories under $XILINX:
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$XILINX/ghdl/unisim
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$XILINX/ghdl/unisim
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$XILINX/ghdl/simprim
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$XILINX/ghdl/simprim
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Two helper scripts will create these libraries:
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Two helper scripts will create these libraries:
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cd $RETROBASE
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cd $RETROBASE
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xtwi xilinx_ghdl_unisim
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xise_ghdl_unisim
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xtwi xilinx_ghdl_simprim
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xise_ghdl_simprim
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If you have several WebPack versions installed, repeat for each version.
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If you have several WebPack versions installed, repeat for each version.
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5. Compile and install the support software -------------------------------
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5. Compile and install the support software -------------------------------
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5a. Compile sharable libraries ---------------------------------------
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5a. Compile sharable libraries ---------------------------------------
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Note: some c++11 features are used in the code
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- N2343: decltype (used by boost bind) -> since gcc 4.3
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- N2431: nullptr -> since gcc 4.6
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- N2930: range based for -> since gcc 4.6
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- N1984: auto-types variables -> since gcc 4.4
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Required tools and libraries:
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Required tools and libraries:
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g++ >= 4.3 (decltype support assumed in usage of boost::bind)
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g++ >= 4.6 (see c++11 usage above)
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boost >= 1.35 (boost::thread api changed, new one is used)
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boost >= 1.35 (boost::thread api changed, new one is used)
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linusb >= 1.0.5 (timerfd support)
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linusb >= 1.0.5 (timerfd support)
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Build was tested under:
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Build was tested under:
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ubuntu lucid (12.04 LTS): gcc 4.6.3 boost 1.46.1 libusb 1.0.9
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ubuntu precise (14.04 LTS): gcc 4.8.2 boost 1.54 libusb 1.0.17
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debian squezze (6.0.6): gcc 4.4.5 boost 1.46.1 libusb 1.0.8
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debian wheezy (7.0.8): gcc 4.7.2 boost 1.49 libusb 1.0.11
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To build all sharable libraries
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To build all sharable libraries
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cd $RETROBASE/tools/src
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cd $RETROBASE/tools/src
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make -j 4
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make -j 4
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cd $HOME
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cd $HOME
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ln -s $RETROBASE/tools/tcl/.tclshrc .
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ln -s $RETROBASE/tools/tcl/.tclshrc .
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ln -s $RETROBASE/tools/tcl/.wishrc .
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ln -s $RETROBASE/tools/tcl/.wishrc .
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5c. Rebuild Cypress FX2 firmware -------------------------------------
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The download includes pre-build firmware images for the Cypress FX2
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USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.
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These firmware images are under
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$RETROBASE/tools/fx2/bin
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To re-build them, e.g. because a different USB VID/PID is to be used
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cd $RETROBASE/tools/fx2/src
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make clean
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make
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make install
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Note: The default build assumes that sdcc with a version 3.x is installed.
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In case sdcc 2.x is installed use
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make SDCC29=1
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instead. See also tools/fx2/src/README.txt in the
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Please read README_USB_VID-PID.txt carefully to understand the usage
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of USB VID and PID.
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6. The build system -------------------------------------------------------
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6. The build system -------------------------------------------------------
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Simulation and synthesis tools usually need a list of the VHDL source
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The generation of
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files, often in proper compilation order (libraries before components).
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- FPGA firmware (e.g. .bit files)
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The different tools have different formats of these 'project files'.
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- test benches (e.g. simulator images)
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is based on make flows.
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The build system employed in this project is based on manifest files called
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'vbom' or "VHDL bill of material" files
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Two design tools are currently supported
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which list for each vhdl source file the libraries and sources for the
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- Xilinx Vivado
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instantiated components, the later via their vbom, and last but not least
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- Artix-7 based board (Basys3, Nexys4)
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the name of the vhdl source file.
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- see README_buildsystem_Vivado.txt
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All file name are relative to the current directory. A recursive traversal
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- Xilinx ISE
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through all vbom's gives for each vhld module all sources needed to compile
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- Spartan-3 and Spartan-6 based boards (S3board, Nexys2, Nexys3)
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it. The vbomconv script in tools/bin does this, and generates depending on
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- see README_buildsystem_ISE.txt
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options
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- make dependency files
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- ISE xst project files
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- ISE ISim project files
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- ghdl commands for analysis, inspection and make step
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The master make files contain pattern rules like
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%.ngc : %.vbom -- synthesize with xst
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% : %.vbom -- build functional model test bench
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which encapsulate all the vbomconf magic
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A full w11a is build from about 100 source files, test benches from
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even more. Using the vbom's a large number of designs can be easily
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maintained.
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6a. Setting up Xilinx environment with xtwi --------------------------
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The Xilinx ISE setup script redefines PATH and LD_LIBRARY_PATH. The ISE
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tools run fine in this environment, but other installed programs on the
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system can (and actually do) fail.
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The build system uses a small wrapper script called xtwi to encapsulate
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the Xilinx environment. It expects that the environment variable XTWI_PATH
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is setup to the install path of the ISE version to be used. Without the
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/ISE_DS/ which is added by the ISE installation procedure !
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Note: don't run the ISE setup scripts ..../settings(32|64).sh in your
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working shell. Setup only XTWI_PATH !
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7. Building test benches --------------------------------------------------
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7. Building test benches --------------------------------------------------
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7a. General instructions ---------------------------------------------
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General instructions are in
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- README_buildsystem_Vivado.txt (for Basys3, Nexys4)
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To compile a test bench named all is needed is
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- README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3)
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make
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The make file will use .vbom, create all make dependency files,
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and generate the needed ghdl commands.
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In many cases the test benches can also be compiled against the gate
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level models derived after the xst, map or par step. To compile them
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make ghdl_tmp_clean
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make _ssim # for post-xst
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make _fsim # for post-map
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make _tsim # for post-par
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The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
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the compilation remains of earlier functional model compiles.
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7b. Available test benches -------------------------------------------
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See file w11a_tb_guide.txt
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8. Building systems -------------------------------------------------------
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8a. General instructions ---------------------------------------------
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First ensure that XTWI_PATH is setup, see section 6a.
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To generate a bit file for a system named all is needed is
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make .bit
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The make file will use .vbom, create all make dependency files, build
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the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce).
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The log files will be named
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_xst.log # xst log file
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_tra.log # translate (ngdbuild) log file (renamed %.bld)
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_map.log # map log file (renamed %_map.mrp)
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_par.log # par log file (renamed %.par)
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_pad.log # pad file (renamed %_pad.txt)
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_twr.log # trce log file (renamed %.twr)
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To load the bitfile with WebPack impact into the target board use
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make .iconfig
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For boards with a Cypress FX2 USB controller load the bitfile directly with
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make .jconfig
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If a svf file is required for configuring the FPGA a svf can be created
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For available test benches see w11a_tb_guide.txt
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from a bit file with
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make .svf
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8. Building systems and configuring FPGAs ---------------------------------
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If only the xst or par output is wanted just use
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General instructions are in
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- README_buildsystem_Vivado.txt (for Basys3, Nexys4)
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make .ngc
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- README_buildsystem_ISE.txt (for S3board, Nexys2, Nexys3)
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make .ncd
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A simple 'message filter' system is also integrated into the make build flow.
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For many (though not all) systems a .mfset file has been provided which
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defines the xst,par and bitgen messages which are considered ok. To see
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only the remaining message extracted from the vaious .log files simply
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use the make target
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make .mfsum
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after a re-build.
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8b. Configuring FPGAs (via make flow) --------------------------------
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The make flow supports also loading the bitstream into FPGAs, either
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via Xilinx Impact, or via the Cypress FX2 USB controller is available.
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For Xilinx Impact a Xilinx USB Cable II has to be properly setup, than
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simply use
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make .iconfig
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For using the Cypress FX2 USB controller on Digilent Nexys2, Nexys3 and
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Atlys boards just connect the USB cable and
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make .jconfig
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This will automatically check and optionaly re-load the FX2 firmware
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to a version matching the FPGA design, generate a .svf file from the
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.bit file, and configure the FPGA. In case the bit file is out-of-date
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the whole design will be re-implemented before.
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8c. Configuring FPGAs (directly via config_wrapper) ------------------
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The make flow described above uses two scripts
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config_wrapper # must be used with xtwi !
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fx2load_wrapper
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which can be used directly for loading available bit or svf files into
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the FPGA. For detailed documentation see the respective man pages.
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Examples for the supported boards are given in section 8e.
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8d. Available systems ------------------------------------------------
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8d. Available systems ------------------------------------------------
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Currently ready to build versions exist for
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Ready to build designs are organized in the directories
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- Digilent S3BOARD (-1000 FPGA version)
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- Digilent Nexys2 board (-1200 FPGA version)
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- Digilent Nexys3 board
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To build the designs locally use
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1. rlink tester
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a. for Digilent S3BOARD
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cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board
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make sys_tst_rlink_s3.bit
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b. for Digilent Nexys2 board
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2
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make sys_tst_rlink_n2.bit
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c. for Digilent Nexys3 board
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$RETROBASE/rtl/sys_gen//
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cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3
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with
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make sys_tst_rlink_n3.bit
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w11a w11a system
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tst_rlink rlink over serial link tester
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tst_rlink_cuff rlink over FX2 interface tester
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and
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basys3 b3: Digilent Basys3 board
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nexys4 n4: Digilent Nexys4 board (cellular RAM version)
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nexys3 n3: Digilent Nexys3 board
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nexys2 n2: Digilent Nexys2 board (-1200 FPGA version)
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s3board s3: Digilent S3board (-1000 FPGA version)
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2. rlink over USB tester
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To build the designs locally use
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a. for Digilent Nexys2 board
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cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic
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make sys_tst_rlink_cuff_ic_n2.bit
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b. for Digilent Nexys3 board
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cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic
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make sys_tst_rlink_cuff_ic_n3.bit
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3. w11a systems
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a. for Digilent S3BOARD
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cd $RETROBASE/rtl/sys_gen/w11a/s3board
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make sys_w11a_s3.bit
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b. for Digilent Nexys2 board
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cd $RETROBASE/rtl/sys_gen/w11a/nexys2
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make sys_w11a_n2.bit
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c. for Digilent Nexys3 board
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cd $RETROBASE/rtl/sys_gen//
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make sys__.bit
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cd $RETROBASE/rtl/sys_gen/w11a/nexys3
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with in most cases = and = 2 letter abriviation for
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make sys_w11a_n3.bit
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the board, e.g. n4 for nexys4.
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8e. Available bitkits with bit and log files -------------------------
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8e. Available bitkits with bit and log files -------------------------
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Tarballs with ready to use bit files and all logfiles from the tool
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Tarballs with ready to use bit files and all logfiles from the tool
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chain can be downloaded from
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chain can be downloaded from
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http://www.retro11.de/data/oc_w11/bitkits/
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http://www.retro11.de/data/oc_w11/bitkits/
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This area is organized in folders for different releases. The tarball
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This area is organized in folders for different releases. The tarball
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file names contain information about release, Xlinix tool, and design:
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file names contain information about release, Xlinix tool, and design:
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__.tgz
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__.tgz
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|
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- Vivado based designs:
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These designs can be loaded with the Vivado hardware server into the FPGA.
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|
|
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- ISE based designs:
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|
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These designs can be loaded with config_wrapper into the FPGA. The
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These designs can be loaded with config_wrapper into the FPGA. The
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procedures for the supported boards are given below.
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procedures for the supported boards are given below.
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Notes:
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Notes:
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1. XTWI_PATH and RETROBASE environment variables must be defined.
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1. XTWI_PATH and RETROBASE environment variables must be defined.
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2. config_wrapper bit2svf is only needed once to create the svf files.
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2. config_wrapper bit2svf is only needed once to create the svf files.
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3. fx2load_wrapper is needed once after each board power on.
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3. fx2load_wrapper is needed once after each board power on.
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a. for Digilent S3BOARD (using ISE Impact)
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a. for Digilent Nexys3 board (using Cypress FX2 USB controller)
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|
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xtwi config_wrapper --board=s3board iconfig .bit
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xtwi config_wrapper --board=nexys3 bit2svf .bit
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fx2load_wrapper --board=nexys3
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xtwi config_wrapper --board=nexys3 jconfig .svf
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|
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b. for Digilent Nexys2 board (using Cypress FX2 USB controller)
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b. for Digilent Nexys2 board (using Cypress FX2 USB controller)
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|
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xtwi config_wrapper --board=nexys2 bit2svf .bit
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xtwi config_wrapper --board=nexys2 bit2svf .bit
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fx2load_wrapper --board=nexys2
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fx2load_wrapper --board=nexys2
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xtwi config_wrapper --board=nexys2 jconfig .svf
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xtwi config_wrapper --board=nexys2 jconfig .svf
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|
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c. for Digilent Nexys3 board (using Cypress FX2 USB controller)
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c. for Digilent S3board (using ISE Impact)
|
|
|
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xtwi config_wrapper --board=s3board iconfig .bit
|
|
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xtwi config_wrapper --board=nexys3 bit2svf .bit
|
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fx2load_wrapper --board=nexys3
|
|
xtwi config_wrapper --board=nexys3 jconfig .svf
|
|
|
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9. Generate Doxygen based source code view --------------------------------
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9. Generate Doxygen based source code view --------------------------------
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|
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Currently there is not much real documentation included in the source
|
Currently there is not much real documentation included in the source
|
files. The doxygen generated html output is nevertheless very useful
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files. The doxygen generated html output is nevertheless very useful
|
