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# -*- tcl -*-
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# -*- tcl -*-
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# $Id: arty_pins.xdc 740 2016-03-06 20:56:56Z mueller $
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# $Id: arty_pins.xdc 758 2016-04-02 18:01:39Z mueller $
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#
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#
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# Copyright 2016- by Walter F.J. Mueller
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# Copyright 2016- by Walter F.J. Mueller
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
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#
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#
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# Pin locks for Digilent Arty core functionality
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# Digilent Arty core functionality
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# - Configuration setup
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# - config voltage
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# - enable bitstream timestamp
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# - Pin Locks for
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# - USB UART
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# - USB UART
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# - human I/O (switches, buttons, leds)
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# - human I/O (switches, buttons, leds)
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2016-04-02 758 1.2 add BITSTREAM.CONFIG.USR_ACCESS setup
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# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config
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# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config
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# 2016-01-31 726 1.0 Initial version
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# 2016-01-31 726 1.0 Initial version
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#
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#
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# config setup --------------------------------------------------------------
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# config setup --------------------------------------------------------------
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set_property CFGBVS VCCO [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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# clocks -- in bank 35 ------------------------------------------------------
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# clocks -- in bank 35 ------------------------------------------------------
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set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
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set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
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