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-- $Id: mt45w8mw16b.vhd 649 2015-02-21 21:10:16Z mueller $
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-- $Id: mt45w8mw16b.vhd 718 2015-12-26 15:59:48Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment
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-- 2011-11-19 427 1.3.2 now numeric_std clean
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-- 2011-11-19 427 1.3.2 now numeric_std clean
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-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
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-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
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-- 2010-06-03 298 1.3 add timing model again
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-- 2010-06-03 298 1.3 add timing model again
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-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
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-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
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-- 2010-05-21 293 1.1 add BCR (only read of default so far)
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-- 2010-05-21 293 1.1 add BCR (only read of default so far)
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signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
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signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
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signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
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signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
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signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
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signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
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signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
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signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
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signal L_ADDR : slv23 := (others=>'0');
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signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access
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signal DOUT_VAL_EN : slbit := '0';
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signal DOUT_VAL_EN : slbit := '0';
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signal DOUT_VAL_AA : slbit := '0';
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signal DOUT_VAL_AA : slbit := '0';
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signal DOUT_VAL_PA : slbit := '0';
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signal DOUT_VAL_PA : slbit := '0';
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signal DOUT_VAL_OE : slbit := '0';
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signal DOUT_VAL_OE : slbit := '0';
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signal DOUT_LZ_CE : slbit := '0';
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signal DOUT_LZ_CE : slbit := '0';
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if ADV = '1' then
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if ADV = '1' then
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L_ADDR <= ADDR;
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L_ADDR <= ADDR;
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end if;
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end if;
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end process proc_adv;
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end process proc_adv;
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-- Notes:
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-- 1. the row change (t_aa) and column change (t_apa) timing depends on the
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-- recognition of address changes and of page changes. To keep the logic
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-- simple L_ADDR and addr_last are initialized with all '1'. This gives
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-- proper behaviour unless the very first access uses the very last
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-- address. In w11a systems, with use only 4 MB, this can't happen, in
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-- most other use cases this is very unlikely.
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proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
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proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
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variable addr_last : slv23 := (others=>'1');
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variable addr_last : slv23 := (others=>'1');-- all '1' for propper 1st access
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begin
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begin
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if (CE'event and CE='1') or
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if (CE'event and CE='1') or
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(BE_L'event and BE_L='1') or
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(BE_L'event and BE_L='1') or
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(BE_U'event and BE_U='1') or
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(BE_U'event and BE_U='1') or
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(WE'event and WE='0') or
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(WE'event and WE='0') or
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