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-- $Id: mt45w8mw16b.vhd 718 2015-12-26 15:59:48Z mueller $
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-- $Id: mt45w8mw16b.vhd 799 2016-08-21 09:20:19Z mueller $
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--
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--
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-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Module Name: mt45w8mw16b - sim
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-- Module Name: mt45w8mw16b - sim
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-- Description: Micron MT45W8MW16B CellularRAM model
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-- Description: Micron MT45W8MW16B CellularRAM model
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-- Currently a much simplified model
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-- Currently a much simplified model
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-- - only async accesses
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-- - only async accesses
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-- - ignores CLK and CRE
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-- - ignores CLK
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-- - simple model for response of DATA lines, but no
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-- - simple model for response of DATA lines, but no
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-- check for timing violations of control lines
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-- check for timing violations of control lines
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
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-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2016-08-18 799 1.4.1 remove 'assert false' from report statements
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-- 2016-07-10 786 1.4 add RCR handling; page mode by default now off !!
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-- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment
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-- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment
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-- 2011-11-19 427 1.3.2 now numeric_std clean
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-- 2011-11-19 427 1.3.2 now numeric_std clean
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-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
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-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
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-- 2010-06-03 298 1.3 add timing model again
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-- 2010-06-03 298 1.3 add timing model again
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-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
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-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
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architecture sim of mt45w8mw16b is
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architecture sim of mt45w8mw16b is
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-- timing constants for -701 speed grade (70 ns; 104 MHz)
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-- timing constants for -701 speed grade (70 ns; 104 MHz)
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constant T_aa : time := 70 ns; -- address access time (max)
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constant T_aa : Delay_length := 70 ns; -- address access time (max)
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constant T_apa : time := 20 ns; -- page acess time (max)
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constant T_apa : Delay_length := 20 ns; -- page access time (max)
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constant T_oh : time := 5 ns; -- output hold from addr change (max)
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constant T_oh : Delay_length := 5 ns; -- output hold from addr change (max)
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constant T_oe : time := 20 ns; -- output enable to valid output (max)
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constant T_oe : Delay_length := 20 ns; -- output enable to valid output (max)
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constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
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constant T_ohz : Delay_length := 8 ns; -- output disable to high-z out (max)
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constant T_olz : time := 3 ns; -- output enable to low-z output (min)
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constant T_olz : Delay_length := 3 ns; -- output enable to low-z output (min)
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constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
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constant T_lz : Delay_length := 10 ns; -- chip enable to low-z output (min)
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constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
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constant T_hz : Delay_length := 8 ns; -- chip disable to high-z output (max)
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constant memsize : positive := 2**(ADDR'length);
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constant memsize : positive := 2**(ADDR'length);
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constant datzero : slv(DATA'range) := (others=>'0');
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constant datzero : slv(DATA'range) := (others=>'0');
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type ram_type is array (0 to memsize-1) of slv(DATA'range);
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type ram_type is array (0 to memsize-1) of slv(DATA'range);
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subtype xcr_f_sel is integer range 19 downto 18; -- cre register select
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constant xcr_sel_rcr : slv2 := "00";
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constant xcr_sel_bcr : slv2 := "10";
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constant bcr_f_mode : integer := 15; -- operating mode
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constant bcr_f_mode : integer := 15; -- operating mode
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constant bcr_f_ilat : integer := 14; -- initial latency
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constant bcr_f_ilat : integer := 14; -- initial latency
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subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
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subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
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constant bcr_f_wp : integer := 10; -- wait polarity
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constant bcr_f_wp : integer := 10; -- wait polarity
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constant bcr_f_wc : integer := 8; -- wait configuration
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constant bcr_f_wc : integer := 8; -- wait configuration
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subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
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subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
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constant bcr_f_bw : integer := 3; -- burst wrap
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constant bcr_f_bw : integer := 3; -- burst wrap
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subtype bcr_f_bl is integer range 2 downto 0; -- burst length
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subtype bcr_f_bl is integer range 2 downto 0; -- burst length
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subtype rcr_f_res3 is integer range 22 downto 20; -- reserved - MBZ
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subtype rcr_f_res2 is integer range 17 downto 8; -- reserved - MBZ
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constant rcr_f_pmode : integer := 7; -- page mode (1=ena)
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subtype rcr_f_res1 is integer range 6 downto 5; -- reserved - MBZ
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constant rcr_f_dpd : integer := 4; -- dpd mode (1=dis)
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constant rcr_f_res0 : integer := 3; -- reserved - MBZ
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subtype rcr_f_par is integer range 2 downto 0; -- array conf (000=all)
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subtype f_byte1 is integer range 15 downto 8;
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subtype f_byte1 is integer range 15 downto 8;
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subtype f_byte0 is integer range 7 downto 0;
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subtype f_byte0 is integer range 7 downto 0;
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signal CE : slbit := '0';
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signal CE : slbit := '0';
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signal OE : slbit := '0';
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signal OE : slbit := '0';
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signal BE_L : slbit := '0';
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signal BE_L : slbit := '0';
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signal BE_U : slbit := '0';
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signal BE_U : slbit := '0';
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signal ADV : slbit := '0';
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signal ADV : slbit := '0';
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signal WE_L_EFF : slbit := '0';
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signal WE_L_EFF : slbit := '0';
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signal WE_U_EFF : slbit := '0';
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signal WE_U_EFF : slbit := '0';
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signal WE_C_EFF : slbit := '0';
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signal R_BCR_MODE : slbit := '1'; -- mode: def: async
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signal R_BCR_MODE : slbit := '1'; -- mode: def: async
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signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
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signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
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signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
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signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
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signal R_BCR_WP : slbit := '1'; -- wp: def: active high
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signal R_BCR_WP : slbit := '1'; -- wp: def: active high
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signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
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signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
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signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
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signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
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signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
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signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
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signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
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signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
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signal R_RCR_PMODE : slbit := '0'; -- pmode:def: disabled (ena=1 !)
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signal R_RCR_DPD : slbit := '1'; -- dpd: def: disabled (ena=0 !)
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signal R_RCR_PAR : slv3 := "000"; -- par: def: full array
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signal R_T_APA_EFF : Delay_length := T_aa; -- page mode disabled by default
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signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access
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signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access
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signal DOUT_VAL_EN : slbit := '0';
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signal DOUT_VAL_EN : slbit := '0';
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signal DOUT_VAL_AA : slbit := '0';
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signal DOUT_VAL_AA : slbit := '0';
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signal DOUT_VAL_PA : slbit := '0';
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signal DOUT_VAL_PA : slbit := '0';
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signal DOUT_VAL_OE : slbit := '0';
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signal DOUT_VAL_OE : slbit := '0';
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WE <= not WE_N;
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WE <= not WE_N;
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BE_L <= not LB_N;
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BE_L <= not LB_N;
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BE_U <= not UB_N;
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BE_U <= not UB_N;
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ADV <= not ADV_N;
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ADV <= not ADV_N;
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WE_L_EFF <= CE and WE and BE_L;
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WE_L_EFF <= CE and WE and BE_L and (not CRE);
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WE_U_EFF <= CE and WE and BE_U;
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WE_U_EFF <= CE and WE and BE_U and (not CRE);
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WE_C_EFF <= CE and WE and CRE;
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-- address valid logic, latch ADDR when ADV true
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-- address valid logic, latch ADDR when ADV true
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proc_adv: process (ADV, ADDR)
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proc_adv: process (ADV, ADDR)
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begin
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begin
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if ADV = '1' then
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if ADV = '1' then
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(WE'event and WE='0') or
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(WE'event and WE='0') or
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(ADV'event and ADV='1') then
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(ADV'event and ADV='1') then
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DOUT_VAL_EN <= '0', '1' after T_aa;
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DOUT_VAL_EN <= '0', '1' after T_aa;
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end if;
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end if;
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if L_ADDR'event then
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if L_ADDR'event then
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DOUT_VAL_PA <= '0', '1' after T_apa;
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DOUT_VAL_PA <= '0', '1' after R_T_APA_EFF;
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if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
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if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
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DOUT_VAL_AA <= '0', '1' after T_aa;
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DOUT_VAL_AA <= '0', '1' after T_aa;
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end if;
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end if;
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addr_last := L_ADDR;
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addr_last := L_ADDR;
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end if;
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end if;
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DOUT_LZ_OE <= '0' after T_ohz;
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DOUT_LZ_OE <= '0' after T_ohz;
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end if;
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end if;
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end if;
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end if;
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end process proc_dout_lz;
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end process proc_dout_lz;
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proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
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proc_cram: process (WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
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variable ram : ram_type := (others=>datzero);
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variable ram : ram_type := (others=>datzero);
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begin
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begin
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-- end of write cycle
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-- end of write cycle
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-- note: to_x01 used below to prevent that 'z' a written into mem.
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-- note: to_x01 used below to prevent that 'z' a written into mem.
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DOUT <= ram(to_integer(unsigned(L_ADDR)));
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DOUT <= ram(to_integer(unsigned(L_ADDR)));
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end process proc_cram;
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end process proc_cram;
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proc_cr: process (WE_C_EFF, L_ADDR)
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begin
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if falling_edge(WE_C_EFF) then
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case L_ADDR(xcr_f_sel) is
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when xcr_sel_rcr =>
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R_RCR_PMODE <= L_ADDR(rcr_f_pmode);
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if L_ADDR(rcr_f_pmode) = '1' then
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R_T_APA_EFF <= T_apa;
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else
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R_T_APA_EFF <= T_aa;
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end if;
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assert L_ADDR(rcr_f_res3) = "000"
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report "bad rcr write: 22:20 not zero" severity error;
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assert L_ADDR(rcr_f_res2) = "0000000000"
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report "bad rcr write: 17: 8 not zero" severity error;
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assert L_ADDR(rcr_f_res1) = "00"
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report "bad rcr write: 6: 5 not zero" severity error;
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assert L_ADDR(rcr_f_dpd) = '1'
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report "bad rcr write: dpd not '1'" severity error;
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assert L_ADDR(rcr_f_res0) = '0'
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report "bad rcr write: 3: 3 not zero" severity error;
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assert L_ADDR(rcr_f_par) = "000"
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report "bad rcr write: par not '000'" severity error;
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when xcr_sel_bcr =>
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report "bcr written - not supported" severity error;
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when others =>
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report "bad select field" severity error;
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end case;
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end if;
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end process proc_cr;
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proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
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proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
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DOUT_LZ_CE, DOUT_LZ_OE)
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DOUT_LZ_CE, DOUT_LZ_OE)
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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begin
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begin
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idout := DOUT;
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idout := DOUT;
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