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-- $Id: nexys2lib.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: nexys2lib.vhd 338 2010-11-13 22:19:25Z mueller $
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--
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--
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Package Name: nexys2lib
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-- Package Name: nexys2lib
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-- Description: Nexys 2 components
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-- Description: Nexys 2 components
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Tool versions: xst 11.4; ghdl 0.26
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-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
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-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
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-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
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-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
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-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
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-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
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-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
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-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
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-- 2010-05-21 292 1.0 Initial version
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-- 2010-05-21 292 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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package nexys2lib is
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package nexys2lib is
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component nexys2_aif is -- NEXYS 2, abstract iface, base
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component nexys2_aif is -- NEXYS 2, abstract iface, base
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port (
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port (
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CLK : in slbit; -- clock
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I_CLK50 : in slbit; -- 50 MHz board clock
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O_CLKSYS : out slbit; -- DCM derived system clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_LED : out slv8; -- s3 leds
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);
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);
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end component;
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end component;
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component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
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component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
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port (
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port (
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CLK : in slbit; -- clock
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I_CLK50 : in slbit; -- 50 MHz board clock
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O_CLKSYS : out slbit; -- DCM derived system clock
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I_RXD : in slbit; -- receive data (board view)
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I_RXD : in slbit; -- receive data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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O_TXD : out slbit; -- transmit data (board view)
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I_SWI : in slv8; -- s3 switches
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I_SWI : in slv8; -- s3 switches
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I_BTN : in slv4; -- s3 buttons
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I_BTN : in slv4; -- s3 buttons
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O_LED : out slv8; -- s3 leds
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O_LED : out slv8; -- s3 leds
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