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# lines to generate the different cases.
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# lines to generate the different cases.
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#
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#
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# libs
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# libs
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../../../vlib/slvtypes.vhd
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../../../vlib/slvtypes.vhd
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../../../vlib/rlink/rlinklib.vbom
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../../../vlib/rlink/rlinklib.vbom
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../../../vlib/rlink/tb/rlinktblib.vhd
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../../../vlib/serport/serportlib.vbom
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../../../vlib/xlib/xlib.vhd
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../../../vlib/xlib/xlib.vhd
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../nexys4lib.vhd
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../nexys4lib.vhd
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../../../vlib/simlib/simlib.vhd
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../../../vlib/simlib/simlib.vhd
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../../../vlib/simlib/simbus.vhd
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../../../vlib/simlib/simbus.vhd
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${sys_conf := sys_conf_sim.vhd}
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${sys_conf := sys_conf_sim.vhd}
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# components
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# components
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../../../vlib/simlib/simclk.vbom
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../../../vlib/simlib/simclk.vbom
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../../../vlib/simlib/simclkcnt.vbom
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../../../vlib/simlib/simclkcnt.vbom
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../../../vlib/rlink/tb/tbcore_rlink.vbom
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../../../vlib/rlink/tbcore/tbcore_rlink.vbom
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../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
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../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
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tb_nexys4_core.vbom
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tb_nexys4_core.vbom
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../../micron/mt45w8mw16b.vbom
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../../micron/mt45w8mw16b.vbom
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../../../vlib/serport/serport_master.vbom
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../../../vlib/serport/tb/serport_master_tb.vbom
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${nexys4_cram_aif := nexys4_cram_dummy.vbom}
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@uut: ${nexys4_cram_aif := nexys4_cram_dummy.vbom}
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# design
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# design
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tb_nexys4_cram.vhd
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tb_nexys4_cram.vhd
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@top:tb_nexys4_cram
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@top:tb_nexys4_cram
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