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-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
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-- $Id: nx_cram_memctl_as.vhd 563 2014-06-22 15:49:09Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- 2010-05-23 293 1.0 Initial version
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-- 2010-05-23 293 1.0 Initial version
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--
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--
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-- Notes:
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-- Notes:
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-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
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-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
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-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
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-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
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-- short READ1 delay works in sim, but not on fpga where the data od the
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-- short READ1 delay works in sim, but not on fpga where the data of the
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-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
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-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
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-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
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-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
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-- 40ns or 50 ns, only T_apa 60 ns fails !
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-- 40ns or 50 ns, only T_apa 60 ns fails !
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-- Unclear what is wrong here, the timing of the memory model seems ok.
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-- Unclear what is wrong here, the timing of the memory model seems ok.
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-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
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-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
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-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
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-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
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-- transition simultaneously. The FPGA will go high-Z quickly, the memory
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-- transition simultaneously. The FPGA will go high-Z quickly, the memory
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-- low-Z delay by the IOB and internal memory delays. No clash.
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-- low-Z delay by the IOB and internal memory delays. No clash.
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-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
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-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
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-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
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-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
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-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
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-- some delay. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
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-- Again no clash due to the 1 cycle delay.
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-- Again no clash due to the 1 cycle delay.
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--
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--
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-- Nominal timings:
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-- Nominal timings:
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-- READ0/1 = N_rd_cycle - 2
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-- READ0/1 = N_rd_cycle - 2
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-- WRITE = N_wr_cycle - 1
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-- WRITE = N_wr_cycle - 1
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