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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [bplib/] [s3board/] [s3_sram_memctl.vhd] - Diff between revs 13 and 29

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-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
--
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
--
-- This program is free software; you may redistribute and/or modify it under
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- the terms of the GNU General Public License as published by the Free
Line 19... Line 19...
--                 vlib/xlib/iob_reg_o_gen
--                 vlib/xlib/iob_reg_o_gen
--                 vlib/xlib/iob_reg_io_gen
--                 vlib/xlib/iob_reg_io_gen
-- Test bench:     tb/tb_s3_sram_memctl
-- Test bench:     tb/tb_s3_sram_memctl
--                 fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
--                 fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
-- Target Devices: generic
-- Target Devices: generic
-- Tool versions:  xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions:  xst 8.2-14.7; ghdl 0.18-0.31
--
--
-- Synthesized (xst):
-- Synthesized (xst):
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- 2010-05-23   293  11.4   L68  xc3s1000-4     7   22    0   14 s  8.5
-- 2010-05-23   293  11.4   L68  xc3s1000-4     7   22    0   14 s  8.5
-- 2008-02-16   116  8.2.03 I34  xc3s1000-4     5   30    0   17 s  7.0
-- 2008-02-16   116  8.2.03 I34  xc3s1000-4     5   30    0   17 s  7.0
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    state : state_type;                 -- state
    state : state_type;                 -- state
    ackr : slbit;                       -- signal ack_r
    ackr : slbit;                       -- signal ack_r
  end record regs_type;
  end record regs_type;
 
 
  constant regs_init : regs_type := (
  constant regs_init : regs_type := (
    s_idle,
    s_idle,                             -- state
    '0'                                 -- ackr
    '0'                                 -- ackr
  );
  );
 
 
  signal R_REGS : regs_type := regs_init;  -- state registers
  signal R_REGS : regs_type := regs_init;  -- state registers
  signal N_REGS : regs_type := regs_init;  -- next value state regs
  signal N_REGS : regs_type := regs_init;  -- next value state regs

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