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-- $Id: ib_intmap.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: pdp11: external interrupt mapper
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-- Description: pdp11: external interrupt mapper
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
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-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
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-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
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-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
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-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
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-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-06-14 56 1.0.1 Use slvtypes.all
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-- 2007-05-12 26 1.0 Initial version
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-- 2007-05-12 26 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.iblib.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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type intp_type is array (15 downto 0) of slv3;
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type intp_type is array (15 downto 0) of slv3;
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type intv_type is array (15 downto 0) of slv9;
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type intv_type is array (15 downto 0) of slv9;
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constant conf_intp : intp_type :=
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constant conf_intp : intp_type :=
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(conv_std_logic_vector(INTMAP(15).pri,3), -- line 15
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(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
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conv_std_logic_vector(INTMAP(14).pri,3), -- line 14
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slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
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conv_std_logic_vector(INTMAP(13).pri,3), -- line 13
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slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
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conv_std_logic_vector(INTMAP(12).pri,3), -- line 12
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slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
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conv_std_logic_vector(INTMAP(11).pri,3), -- line 11
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slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
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conv_std_logic_vector(INTMAP(10).pri,3), -- line 10
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slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
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conv_std_logic_vector(INTMAP( 9).pri,3), -- line 9
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slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
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conv_std_logic_vector(INTMAP( 8).pri,3), -- line 8
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slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
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conv_std_logic_vector(INTMAP( 7).pri,3), -- line 7
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slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
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conv_std_logic_vector(INTMAP( 6).pri,3), -- line 6
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slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
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conv_std_logic_vector(INTMAP( 5).pri,3), -- line 5
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slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
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conv_std_logic_vector(INTMAP( 4).pri,3), -- line 4
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slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
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conv_std_logic_vector(INTMAP( 3).pri,3), -- line 3
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slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
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conv_std_logic_vector(INTMAP( 2).pri,3), -- line 2
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slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
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conv_std_logic_vector(INTMAP( 1).pri,3), -- line 1
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slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
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conv_std_logic_vector( 0,3) -- line 0 (always 0 !!)
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slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
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);
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);
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constant conf_intv : intv_type :=
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constant conf_intv : intv_type :=
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(conv_std_logic_vector(INTMAP(15).vec,9), -- line 15
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(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
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conv_std_logic_vector(INTMAP(14).vec,9), -- line 14
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slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
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conv_std_logic_vector(INTMAP(13).vec,9), -- line 13
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slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
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conv_std_logic_vector(INTMAP(12).vec,9), -- line 12
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slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
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conv_std_logic_vector(INTMAP(11).vec,9), -- line 11
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slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
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conv_std_logic_vector(INTMAP(10).vec,9), -- line 10
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slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
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conv_std_logic_vector(INTMAP( 9).vec,9), -- line 9
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slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
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conv_std_logic_vector(INTMAP( 8).vec,9), -- line 8
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slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
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conv_std_logic_vector(INTMAP( 7).vec,9), -- line 7
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slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
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conv_std_logic_vector(INTMAP( 6).vec,9), -- line 6
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slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
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conv_std_logic_vector(INTMAP( 5).vec,9), -- line 5
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slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
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conv_std_logic_vector(INTMAP( 4).vec,9), -- line 4
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slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
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conv_std_logic_vector(INTMAP( 3).vec,9), -- line 3
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slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
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conv_std_logic_vector(INTMAP( 2).vec,9), -- line 2
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slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
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conv_std_logic_vector(INTMAP( 1).vec,9), -- line 1
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slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
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conv_std_logic_vector( 0,9) -- line 0 (always 0 !!)
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slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
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);
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);
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-- attribute PRIORITY_EXTRACT : string;
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-- attribute PRIORITY_EXTRACT : string;
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-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
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-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
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proc_intmap : process (EI_LINE, EI_ACKM)
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proc_intmap : process (EI_LINE, EI_ACKM)
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variable iline : integer := 0;
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variable iline : integer := 0;
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variable iei_ack : slv16 := (others=>'0');
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variable iei_ack : slv16 := (others=>'0');
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begin
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begin
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iline := conv_integer(unsigned(EI_LINE));
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iline := to_integer(unsigned(EI_LINE));
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iei_ack := (others=>'0');
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iei_ack := (others=>'0');
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if EI_ACKM = '1' then
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if EI_ACKM = '1' then
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iei_ack(iline) := '1';
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iei_ack(iline) := '1';
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end if;
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end if;
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