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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [ibus/] [ibdr_dl11.vhd] - Diff between revs 9 and 13

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Rev 9 Rev 13
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-- $Id: ibdr_dl11.vhd 350 2010-12-28 16:40:11Z mueller $
-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
--
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
--
-- This program is free software; you may redistribute and/or modify it under
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
-- Software Foundation, either version 2, or at your option any later version.
--
--
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-- Description:    ibus dev(rem): DL11-A/B
-- Description:    ibus dev(rem): DL11-A/B
--
--
-- Dependencies:   -
-- Dependencies:   -
-- Test bench:     -
-- Test bench:     -
-- Target Devices: generic
-- Target Devices: generic
-- Tool versions:  xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
-- Tool versions:  xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
--
-- Synthesized (xst):
-- Synthesized (xst):
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- 2010-10-17   333 12.1    M53d xc3s1000-4    39  126    0   72 s  7.6
-- 2010-10-17   333 12.1    M53d xc3s1000-4    39  126    0   72 s  7.6
-- 2009-07-12   233 10.1.03 K39  xc3s1000-4    38  119    0   69 s  6.3
-- 2009-07-12   233 10.1.03 K39  xc3s1000-4    38  119    0   69 s  6.3
-- 2009-07-11   232 10.1.03 K39  xc3s1000-4    23   61    0   40 s  5.5
-- 2009-07-11   232 10.1.03 K39  xc3s1000-4    23   61    0   40 s  5.5
--
--
-- Revision History: 
-- Revision History: 
-- Date         Rev Version  Comment
-- Date         Rev Version  Comment
 
-- 2011-11-18   427   1.2.2  now numeric_std clean
-- 2010-10-23   335   1.2.1  rename RRI_LAM->RB_LAM;
-- 2010-10-23   335   1.2.1  rename RRI_LAM->RB_LAM;
-- 2010-10-17   333   1.2    use ibus V2 interface
-- 2010-10-17   333   1.2    use ibus V2 interface
-- 2010-06-11   303   1.1    use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-11   303   1.1    use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12   233   1.0.5  add RESET, CE_USEC port; implement input rate limit
-- 2009-07-12   233   1.0.5  add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22   161   1.0.6  use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-08-22   161   1.0.6  use iblib; add EI_ACK_* to proc_next sens. list
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-- 2008-01-05   108   1.0    Initial version 
-- 2008-01-05   108   1.0    Initial version 
------------------------------------------------------------------------------
------------------------------------------------------------------------------
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
 
use work.slvtypes.all;
use work.slvtypes.all;
use work.iblib.all;
use work.iblib.all;
 
 
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is                     -- ibus dev(rem): DL11-A/B
entity ibdr_dl11 is                     -- ibus dev(rem): DL11-A/B
  generic (
  generic (
    IB_ADDR : slv16 := conv_std_logic_vector(8#177560#,16));
    IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
  port (
  port (
    CLK : in slbit;                     -- clock
    CLK : in slbit;                     -- clock
    CE_USEC : in slbit;                 -- usec pulse
    CE_USEC : in slbit;                 -- usec pulse
    RESET : in slbit;                   -- system reset
    RESET : in slbit;                   -- system reset
    BRESET : in slbit;                  -- ibus reset
    BRESET : in slbit;                  -- ibus reset
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begin
begin
 
 
  proc_regs: process (CLK)
  proc_regs: process (CLK)
  begin
  begin
    if CLK'event and CLK='1' then
    if rising_edge(CLK) then
      if BRESET = '1' then
      if BRESET = '1' then
        R_REGS <= regs_init;
        R_REGS <= regs_init;
        if RESET = '0' then               -- if RESET=0 we do just an ibus reset
        if RESET = '0' then               -- if RESET=0 we do just an ibus reset
          R_REGS.rrlim   <= N_REGS.rrlim;   -- don't reset rx rate limit
          R_REGS.rrlim   <= N_REGS.rrlim;   -- don't reset rx rate limit
          R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
          R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
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      n.rdlycnt := rdlyinit;                  -- init counter
      n.rdlycnt := rdlyinit;                  -- init counter
      if r.rrlim /= "000" then                -- rate limiter enabled ?
      if r.rrlim /= "000" then                -- rate limiter enabled ?
        n.rdlybsy := '1';                       -- set busy 
        n.rdlybsy := '1';                       -- set busy 
      end if;
      end if;
    elsif CE_USEC = '1' then                -- if end-of-usec
    elsif CE_USEC = '1' then                -- if end-of-usec
      n.rdlycnt := unsigned(r.rdlycnt) - 1;   -- decrement
      n.rdlycnt := slv(unsigned(r.rdlycnt) - 1);   -- decrement
      if r.rdlybsy='1' and                   -- if delay busy
      if r.rdlybsy='1' and                   -- if delay busy
          unsigned(r.rdlycnt) = 0 then        --   and counter at zero
          unsigned(r.rdlycnt) = 0 then        --   and counter at zero
        n.rdlybsy := '0';                       -- clear busy
        n.rdlybsy := '0';                       -- clear busy
        if n.rval = '1' then                    -- if rbuf is valid or is set
        if n.rval = '1' then                    -- if rbuf is valid or is set
                                                --   valid this cycle (use n.!!)
                                                --   valid this cycle (use n.!!)

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