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-- $Id: ibdr_maxisys.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ibdr_maxisys.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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| Line 25... |
Line 25... |
-- ib_sres_or_4
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-- ib_sres_or_4
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-- ib_sres_or_3
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-- ib_sres_or_3
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-- ib_intmap
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-- ib_intmap
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53 xc3s1000-4 312 1058 16 617 s 10.3
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-- 2010-10-17 314 12.1 M53 xc3s1000-4 300 1094 16 626 s 10.4
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
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-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
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-- 2009-06-20 227 1.0.3 rename generate labels.
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-- 2009-06-20 227 1.0.3 rename generate labels.
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-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces
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-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces
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-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist
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-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist
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| Line 77... |
Line 84... |
CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_USEC : in slbit; -- usec pulse
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CE_USEC : in slbit; -- usec pulse
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RRI_LAM : out slv16_1; -- remote attention vector
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RB_LAM : out slv16_1; -- remote attention vector
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_PRI : out slv3; -- interrupt priority (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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EI_VECT : out slv9_2; -- interrupt vector (to cpu)
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| Line 108... |
Line 115... |
(8#074#,4), -- line 2 PC11-PTP
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(8#074#,4), -- line 2 PC11-PTP
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(8#200#,4), -- line 1 LP11
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(8#200#,4), -- line 1 LP11
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intmap_init -- line 0
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intmap_init -- line 0
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);
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);
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signal RRI_LAM_DENUA : slbit := '0';
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signal RB_LAM_DENUA : slbit := '0';
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signal RRI_LAM_RP06 : slbit := '0';
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signal RB_LAM_RP06 : slbit := '0';
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signal RRI_LAM_RL11 : slbit := '0';
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signal RB_LAM_RL11 : slbit := '0';
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signal RRI_LAM_RK11 : slbit := '0';
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signal RB_LAM_RK11 : slbit := '0';
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signal RRI_LAM_TM11 : slbit := '0';
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signal RB_LAM_TM11 : slbit := '0';
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signal RRI_LAM_DZ11 : slbit := '0';
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signal RB_LAM_DZ11 : slbit := '0';
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signal RRI_LAM_DL11_0 : slbit := '0';
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signal RB_LAM_DL11_0 : slbit := '0';
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signal RRI_LAM_DL11_1 : slbit := '0';
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signal RB_LAM_DL11_1 : slbit := '0';
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signal RRI_LAM_PC11 : slbit := '0';
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signal RB_LAM_PC11 : slbit := '0';
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signal RRI_LAM_LP11 : slbit := '0';
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signal RB_LAM_LP11 : slbit := '0';
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signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
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signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
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signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init;
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signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init;
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| Line 229... |
Line 236... |
I0 : ibdr_rk11
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I0 : ibdr_rk11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_MSEC => CE_MSEC,
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CE_MSEC => CE_MSEC,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_RK11,
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RB_LAM => RB_LAM_RK11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_RK11,
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IB_SRES => IB_SRES_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_REQ => EI_REQ_RK11,
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EI_ACK => EI_ACK_RK11
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EI_ACK => EI_ACK_RK11
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);
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);
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| Line 243... |
Line 250... |
port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_DL11_0,
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RB_LAM => RB_LAM_DL11_0,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_DL11_0,
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IB_SRES => IB_SRES_DL11_0,
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EI_REQ_RX => EI_REQ_DL11RX_0,
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EI_REQ_RX => EI_REQ_DL11RX_0,
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EI_REQ_TX => EI_REQ_DL11TX_0,
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EI_REQ_TX => EI_REQ_DL11TX_0,
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EI_ACK_RX => EI_ACK_DL11RX_0,
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EI_ACK_RX => EI_ACK_DL11RX_0,
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| Line 262... |
Line 269... |
port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CE_USEC => CE_USEC,
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CE_USEC => CE_USEC,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_DL11_1,
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RB_LAM => RB_LAM_DL11_1,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_DL11_1,
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IB_SRES => IB_SRES_DL11_1,
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EI_REQ_RX => EI_REQ_DL11RX_1,
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EI_REQ_RX => EI_REQ_DL11RX_1,
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EI_REQ_TX => EI_REQ_DL11TX_1,
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EI_REQ_TX => EI_REQ_DL11TX_1,
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EI_ACK_RX => EI_ACK_DL11RX_1,
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EI_ACK_RX => EI_ACK_DL11RX_1,
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| Line 279... |
Line 286... |
I0 : ibdr_pc11
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I0 : ibdr_pc11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_PC11,
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RB_LAM => RB_LAM_PC11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_PC11,
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IB_SRES => IB_SRES_PC11,
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EI_REQ_PTR => EI_REQ_PC11PTR,
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EI_REQ_PTR => EI_REQ_PC11PTR,
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EI_REQ_PTP => EI_REQ_PC11PTP,
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EI_REQ_PTP => EI_REQ_PC11PTP,
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EI_ACK_PTR => EI_ACK_PC11PTR,
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EI_ACK_PTR => EI_ACK_PC11PTR,
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| Line 296... |
Line 303... |
I0 : ibdr_lp11
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I0 : ibdr_lp11
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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BRESET => BRESET,
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BRESET => BRESET,
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RRI_LAM => RRI_LAM_LP11,
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RB_LAM => RB_LAM_LP11,
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IB_MREQ => IB_MREQ,
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IB_MREQ => IB_MREQ,
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IB_SRES => IB_SRES_LP11,
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IB_SRES => IB_SRES_LP11,
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EI_REQ => EI_REQ_LP11,
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EI_REQ => EI_REQ_LP11,
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EI_ACK => EI_ACK_LP11
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EI_ACK => EI_ACK_LP11
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);
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);
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| Line 397... |
Line 404... |
EI_ACK_DL11TX_1 <= EI_ACK( 4);
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EI_ACK_DL11TX_1 <= EI_ACK( 4);
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EI_ACK_PC11PTR <= EI_ACK( 3);
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EI_ACK_PC11PTR <= EI_ACK( 3);
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EI_ACK_PC11PTP <= EI_ACK( 2);
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EI_ACK_PC11PTP <= EI_ACK( 2);
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EI_ACK_LP11 <= EI_ACK( 1);
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EI_ACK_LP11 <= EI_ACK( 1);
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RRI_LAM(15 downto 11) <= (others=>'0');
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RB_LAM(15 downto 11) <= (others=>'0');
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RRI_LAM(10) <= RRI_LAM_PC11;
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RB_LAM(10) <= RB_LAM_PC11;
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RRI_LAM( 9) <= RRI_LAM_DENUA;
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RB_LAM( 9) <= RB_LAM_DENUA;
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RRI_LAM( 8) <= RRI_LAM_LP11;
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RB_LAM( 8) <= RB_LAM_LP11;
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RRI_LAM( 7) <= RRI_LAM_TM11;
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RB_LAM( 7) <= RB_LAM_TM11;
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RRI_LAM( 6) <= RRI_LAM_RP06;
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RB_LAM( 6) <= RB_LAM_RP06;
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RRI_LAM( 5) <= RRI_LAM_RL11;
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RB_LAM( 5) <= RB_LAM_RL11;
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RRI_LAM( 4) <= RRI_LAM_RK11;
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RB_LAM( 4) <= RB_LAM_RK11;
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RRI_LAM( 3) <= RRI_LAM_DZ11;
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RB_LAM( 3) <= RB_LAM_DZ11;
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RRI_LAM( 2) <= RRI_LAM_DL11_1;
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RB_LAM( 2) <= RB_LAM_DL11_1;
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RRI_LAM( 1) <= RRI_LAM_DL11_0;
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RB_LAM( 1) <= RB_LAM_DL11_0;
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end syn;
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end syn;
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No newline at end of file
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No newline at end of file
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