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-- $Id: ibdr_rk11.vhd 317 2010-07-22 19:36:56Z mueller $
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-- $Id: ibdr_rk11.vhd 335 2010-10-24 22:24:23Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Description: ibus dev(rem): RK11-A/B
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-- Description: ibus dev(rem): RK11-A/B
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--
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--
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-- Dependencies: ram_1swar_gen
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-- Dependencies: ram_1swar_gen
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-10-17 333 12.1 M53 xc3s1000-4 46 248 16 137 s 7.2
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-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
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-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
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-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
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-- 2010-10-17 333 1.2 use ibus V2 interface
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
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-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
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-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
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-- BUGFIX: sector counter now counts 000,...,013.
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-- BUGFIX: sector counter now counts 000,...,013.
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-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
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-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
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-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
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-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
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-- fixed address: 177400
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-- fixed address: 177400
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- msec pulse
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CE_MSEC : in slbit; -- msec pulse
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BRESET : in slbit; -- ibus reset
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BRESET : in slbit; -- ibus reset
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RRI_LAM : out slbit; -- remote attention
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RB_LAM : out slbit; -- remote attention
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_MREQ : in ib_mreq_type; -- ibus request
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IB_SRES : out ib_sres_type; -- ibus response
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IB_SRES : out ib_sres_type; -- ibus response
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EI_REQ : out slbit; -- interrupt request
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EI_REQ : out slbit; -- interrupt request
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EI_ACK : in slbit -- interrupt acknowledge
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EI_ACK : in slbit -- interrupt acknowledge
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);
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);
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s_idle,
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s_idle,
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s_init
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s_init
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);
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);
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type regs_type is record -- state registers
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type regs_type is record -- state registers
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ibsel : slbit; -- ibus select
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state : state_type; -- state
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state : state_type; -- state
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id : slv3; -- rkds: drive id of search done
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id : slv3; -- rkds: drive id of search done
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sc : slv4; -- rkds: sector counter
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sc : slv4; -- rkds: sector counter
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cse : slbit; -- rker: check sum error
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cse : slbit; -- rker: check sum error
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wce : slbit; -- rker: write check error
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wce : slbit; -- rker: write check error
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creset : slbit; -- control reset flag
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creset : slbit; -- control reset flag
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crdone : slbit; -- control reset done since last fdone
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crdone : slbit; -- control reset done since last fdone
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_init, --
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'0', -- ibsel
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s_init, -- state
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(others=>'0'), -- id
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(others=>'0'), -- id
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(others=>'0'), -- sc
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(others=>'0'), -- sc
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'0','0', -- cse, wce
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'0','0', -- cse, wce
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'0','0','0', -- he, scp, maint
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'0','0','0', -- he, scp, maint
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'1', -- rdy (SET TO 1)
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'1', -- rdy (SET TO 1)
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end process proc_regs;
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end process proc_regs;
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proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
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proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
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variable r : regs_type := regs_init;
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ibsel : slbit := '0';
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variable ibhold : slbit := '0';
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variable ibbusy : slbit := '0';
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variable icrip : slbit := '0';
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variable icrip : slbit := '0';
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variable idout : slv16 := (others=>'0');
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variable idout : slv16 := (others=>'0');
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variable ibrd : slbit := '0';
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variable ibrem : slbit := '0';
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variable ibrem : slbit := '0';
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variable ibreq : slbit := '0';
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variable ibrd : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw0 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ibw1 : slbit := '0';
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variable ibwrem : slbit := '0';
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variable ibwrem : slbit := '0';
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variable ilam : slbit := '0';
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variable ilam : slbit := '0';
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variable iscval : slbit := '0';
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variable iscval : slbit := '0';
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begin
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begin
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r := R_REGS;
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r := R_REGS;
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n := R_REGS;
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n := R_REGS;
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ibsel := '0';
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ibhold := '0';
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ibbusy := '0';
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icrip := '0';
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icrip := '0';
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idout := (others=>'0');
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idout := (others=>'0');
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ibrd := not IB_MREQ.we;
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ibrem := IB_MREQ.racc or r.maint;
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ibrem := IB_MREQ.racc or r.maint;
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ibreq := IB_MREQ.re or IB_MREQ.we;
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ibrd := IB_MREQ.re;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw0 := IB_MREQ.we and IB_MREQ.be0;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ibw1 := IB_MREQ.we and IB_MREQ.be1;
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ibwrem := IB_MREQ.we and ibrem;
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ibwrem := IB_MREQ.we and ibrem;
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ilam := '0';
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ilam := '0';
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iscval := '0';
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iscval := '0';
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imem_we1 := '0';
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imem_we1 := '0';
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imem_addr := '0' & IB_MREQ.addr(3 downto 1);
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imem_addr := '0' & IB_MREQ.addr(3 downto 1);
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imem_din := IB_MREQ.din;
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imem_din := IB_MREQ.din;
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-- ibus address decoder
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-- ibus address decoder
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if IB_MREQ.req = '1' and
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n.ibsel := '0';
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if IB_MREQ.aval = '1' and
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IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
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IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
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ibsel := '1';
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n.ibsel := '1';
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end if;
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end if;
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-- internal state machine (for control reset)
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-- internal state machine (for control reset)
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case r.state is
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case r.state is
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when s_idle =>
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when s_idle =>
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null;
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null;
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when s_init =>
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when s_init =>
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ibbusy := ibsel; -- keep req pending if selected
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ibhold := r.ibsel; -- hold ibus when controller busy
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ibsel := '0'; -- but don't process selection
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icrip := '1';
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icrip := '1';
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n.icnt := unsigned(r.icnt) + 1;
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n.icnt := unsigned(r.icnt) + 1;
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if unsigned(r.icnt) = 7 then
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if unsigned(r.icnt) = 7 then
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n.state := s_idle;
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n.state := s_idle;
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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-- ibus transactions
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-- ibus transactions
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if ibsel = '1' then
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if r.ibsel='1' and ibhold='0' then -- selected and not holding
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idout := MEM_DOUT;
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idout := MEM_DOUT;
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imem_we0 := ibw0;
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imem_we0 := ibw0;
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imem_we1 := ibw1;
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imem_we1 := ibw1;
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case IB_MREQ.addr(3 downto 1) is
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case IB_MREQ.addr(3 downto 1) is
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Line 466... |
MEM_1_WE <= imem_we1;
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MEM_1_WE <= imem_we1;
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MEM_ADDR <= imem_addr;
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MEM_ADDR <= imem_addr;
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MEM_DIN <= imem_din;
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MEM_DIN <= imem_din;
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IB_SRES.dout <= idout;
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IB_SRES.dout <= idout;
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IB_SRES.ack <= ibsel;
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IB_SRES.ack <= r.ibsel and ibreq;
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IB_SRES.busy <= ibbusy;
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IB_SRES.busy <= ibhold and ibreq;
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RRI_LAM <= ilam;
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RB_LAM <= ilam;
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EI_REQ <= iei_req;
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EI_REQ <= iei_req;
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end process proc_next;
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end process proc_next;
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