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Line 1... Line 1... 
-- $Id: fifo_2c_dram.vhd 649 2015-02-21 21:10:16Z mueller $
 
-- $Id: fifo_2c_dram2.vhd 752 2016-03-27 17:57:18Z mueller $
 
--
 
--
 
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 
--
 
--
 
-- This program is free software; you may redistribute and/or modify it under
 
-- This program is free software; you may redistribute and/or modify it under
 
-- the terms of the GNU General Public License as published by the Free
 
-- the terms of the GNU General Public License as published by the Free
 
-- Software Foundation, either version 2, or at your option any later version.
 
-- Software Foundation, either version 2, or at your option any later version.
 
--
 
--
Line 10... Line 10... 
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
 
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
 
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
-- for complete details.
 
-- for complete details.
 
--
 
--
 
------------------------------------------------------------------------------
 
------------------------------------------------------------------------------
 
-- Module Name:    fifo_2c_dram - syn
 
-- Module Name:    fifo_2c_dram2 - syn
 
-- Description:    FIFO, two clock domain, distributed RAM based, with
 
-- Description:    FIFO, two clock domain, distributed RAM based, with
 
--                 enable/busy/valid/hold interface.
 
--                 enable/busy/valid/hold interface.
 
--
 
--
 
-- Dependencies:   ram_1swar_1ar_gen
 
-- Dependencies:   ram_1swar_1ar_gen
 
--                 genlib/gray_cnt_n
 
--                 genlib/gray_cnt_n
 
--                 genlib/gray2bin_gen
 
--                 genlib/gray2bin_gen
 
--
 
--
 
-- Test bench:     tb/tb_fifo_2c_dram
 
-- Test bench:     tb/tb_fifo_2c_dram
 
-- Target Devices: generic Spartan, Virtex
 
-- Target Devices: generic
 
-- Tool versions:  xst 8.2-14.7; ghdl 0.18-0.31
 
-- Tool versions:  viv 2015.4; ghdl 0.33
 
-- Revision History: 
-- Revision History: 
-- Date         Rev Version  Comment
 
-- Date         Rev Version  Comment
 
-- 2011-11-13   424   1.1    use capture+sync flops; reset now glitch free 
-- 2016-03-24   751   1.0    Initial version (derived from fifo_2c_dram, is
 
-- 2011-11-07   421   1.0.2  now numeric_std clean
 
--                             exactly same logic, re-written to allow proper
 
-- 2007-12-28   107   1.0.1  VAL=0 in cycle after RESETR=1
 
--                             usage of vivado constraints)
 
-- 2007-12-28   106   1.0    Initial version
 
 
 
--
 
 
 
-- Some synthesis results:
 
 
 
-- - 2011-11-13 Rev 424: ise 13.1   for xc3s1000-ft256-4:
 
 
 
--   AWIDTH DWIDTH  LUT.l LUT.m LUT.s Flop Slice  CLKW    CLKR (xst est.)
 
 
 
--        4     16     41    32    12   38    54  135MHz  115MHz    ( 16 words)
 
 
 
--        5     16     65    64    14   40    80  113MHz  116MHz    ( 32 words)
 
 
 
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
 
 
 
--   AWIDTH DWIDTH  LUT.l LUT.m  Flop   CLKW    CLKR (xst est.)
 
 
 
--        4     16     40    32    42   141MHz  165MHz    ( 16 words)
 
 
 
--        5     16     65    64    52   108MHz  108MHz    ( 32 words)
 
 
 
--        6     16     95   128    61   111MHz  113MHz    ( 64 words)
 
 
 
--        7     16    149   256    74   100MHz   96MHz    (128 words)
 
 
 
------------------------------------------------------------------------------
 
------------------------------------------------------------------------------
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
use ieee.numeric_std.all;
 
 
 
 
 
use work.slvtypes.all;
 
use work.slvtypes.all;
 
use work.genlib.all;
 
use work.genlib.all;
 
use work.memlib.all;
 
use work.memlib.all;
 
 
 
 
 
entity fifo_2c_dram is                  -- fifo, 2 clock, dram based
 
entity fifo_2c_dram2 is                 -- fifo, 2 clock, dram based (v2)
 
  generic (
 
  generic (
 
    AWIDTH : positive :=  5;            -- address width (sets size)
 
    AWIDTH : positive :=  5;            -- address width (sets size)
 
    DWIDTH : positive := 16);           -- data width
 
    DWIDTH : positive := 16);           -- data width
 
  port (
 
  port (
 
    CLKW : in slbit;                    -- clock (write side)
 
    CLKW : in slbit;                    -- clock (write side)
Line 67... Line 54... 
    VAL : out slbit;                    -- R|read valid
 
    VAL : out slbit;                    -- R|read valid
 
    HOLD : in slbit;                    -- R|read hold
 
    HOLD : in slbit;                    -- R|read hold
 
    SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
 
    SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
 
    SIZER : out slv(AWIDTH-1 downto 0)  -- R|number slots to read 
    SIZER : out slv(AWIDTH-1 downto 0)  -- R|number slots to read 
  );
 
  );
 
end fifo_2c_dram;
 
end fifo_2c_dram2;
 
 
 
 
 
 
 
 
 
architecture syn of fifo_2c_dram is
 
architecture syn of fifo_2c_dram2 is
 
 
 
 
 
  type regw_type is record
 
  subtype a_range is integer range AWIDTH-1 downto  0;   -- addr value regs
 
    raddr_c : slv(AWIDTH-1 downto 0);   -- read address (capt from CLKR)
 
 
 
    raddr_s : slv(AWIDTH-1 downto 0);   -- read address (sync in CLKW)
 
 
 
    sizew : slv(AWIDTH-1 downto 0);     -- slots to write
 
 
 
    busy : slbit;                       -- busy flag
 
 
 
    rstw : slbit;                       -- resetw active
 
 
 
    rstw_sc : slbit;                    -- resetw (sync-capt from CLKR-CLKW)
 
 
 
    rstw_ss : slbit;                    -- resetw (sync-sync from CLKR-CLKW)
 
 
 
    rstr_c : slbit;                     -- resetr (capt from CLKR)
 
 
 
    rstr_s : slbit;                     -- resetr (sync from CLKR)
 
 
 
  end record regw_type;
 
 
 
 
 
 
 
  constant regw_init : regw_type := (
 
 
 
    slv(to_unsigned(0,AWIDTH)),         -- raddr_c
 
 
 
    slv(to_unsigned(0,AWIDTH)),         -- raddr_s
 
 
 
    slv(to_unsigned(0,AWIDTH)),         -- sizew
 
 
 
    '0',                                -- busy
 
 
 
    '0','0','0',                        -- rstw,rstw_sc,rstw_ss
 
 
 
    '0','0'                             -- rstr_c,rstr_s
 
 
 
  );
 
 
 
 
 
 
 
  type regr_type is record
 
  signal RW_RADDR_S0 :  slv(a_range) := (others=>'0'); -- read addr: CLKR->CLKW
 
    waddr_c : slv(AWIDTH-1 downto 0);   -- write address (capt from CLKW)
 
  signal RW_RADDR_S1 :  slv(a_range) := (others=>'0'); -- read addr: CLKW->CLKW
 
    waddr_s : slv(AWIDTH-1 downto 0);   -- write address (sync in CLKR)
 
  signal RW_SIZEW :     slv(a_range) := (others=>'0'); -- slots to write
 
    sizer : slv(AWIDTH-1 downto 0);     -- slots to read
 
  signal RW_BUSY :      slbit        := '0';           -- busy flag
 
    val : slbit;                        -- valid flag
 
  signal RW_RSTW :      slbit        := '0';           -- resetw active
 
    rstr : slbit;                       -- resetr active
 
  signal RW_RSTW_E_S0 : slbit        := '0';           -- rstw-echo: CLKR->CLKW
 
    rstr_sc : slbit;                    -- resetr (sync-capt from CLKW-CLKR)
 
  signal RW_RSTW_E_S1 : slbit        := '0';           -- rstw-echo: CLKW->CLKW
 
    rstr_ss : slbit;                    -- resetr (sync-sync from CLKW-CLKR)
 
  signal RW_RSTR_S0 :   slbit        := '0';           -- resetr: CLKR->CLKW
 
    rstw_c : slbit;                     -- resetw (capt from CLKW)
 
  signal RW_RSTR_S1 :   slbit        := '0';           -- resetr: CLKW->CLKW
 
    rstw_s : slbit;                     -- resetw (sync from CLKW)
 
 
 
  end record regr_type;
 
  signal NW_SIZEW :     slv(a_range) := (others=>'0'); -- slots to write
 
 
 
  signal NW_BUSY :      slbit        := '0';           -- busy flag
 
  constant regr_init : regr_type := (
 
  signal NW_RSTW :      slbit        := '0';           -- resetw active
 
    slv(to_unsigned(0,AWIDTH)),         -- waddr_c
 
 
 
    slv(to_unsigned(0,AWIDTH)),         -- waddr_s
 
  signal RR_WADDR_S0 :  slv(a_range) := (others=>'0'); -- write addr: CLKW->CLKR
 
    slv(to_unsigned(0,AWIDTH)),         -- sizer
 
  signal RR_WADDR_S1 :  slv(a_range) := (others=>'0'); -- write addr: CLKR->CLKR
 
    '0',                                -- val
 
  signal RR_SIZER :     slv(a_range) := (others=>'0'); -- slots to read
 
    '0','0','0',                        -- rstr,rstr_sc,rstr_ss
 
  signal RR_VAL:        slbit        := '0';           -- valid flag
 
    '0','0'                             -- rstw_c,rstw_s
 
  signal RR_RSTR :      slbit        := '0';           -- resetr active
 
  );
 
  signal RR_RSTR_E_S0 : slbit        := '0';           -- rstr-echo: CLKW->CLKR
 
 
 
  signal RR_RSTR_E_S1 : slbit        := '0';           -- rstr-echo: CLKR->CLKR
 
  signal R_REGW : regw_type := regw_init;  -- write side state registers
 
  signal RR_RSTW_S0 :   slbit        := '0';           -- resetw: CLKW->CLKR
 
  signal N_REGW : regw_type := regw_init;  -- next values write side
 
  signal RR_RSTW_S1 :   slbit        := '0';           -- resetw: CLKR->CLKR
 
  signal R_REGR : regr_type := regr_init;  -- read  side state registers
 
 
 
  signal N_REGR : regr_type := regr_init;  -- next values read  side
 
  signal NR_SIZER :    slv(a_range) := (others=>'0'); -- slots to read
 
 
 
  signal NR_VAL:       slbit        := '0';           -- valid flag
 
 
 
  signal NR_RSTR :     slbit        := '0';           -- resetr active
 
 
 
 
 
  signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal WADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal WADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
  signal RADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
 
 
 
 
 
  signal GCW_RST : slbit := '0';
 
  signal GCW_RST : slbit := '0';
 
  signal GCW_CE : slbit := '0';
 
  signal GCW_CE : slbit := '0';
 
  signal GCR_RST : slbit := '0';
 
  signal GCR_RST : slbit := '0';
 
  signal GCR_CE : slbit := '0';
 
  signal GCR_CE : slbit := '0';
 
 
 
 
 
 
 
  attribute ASYNC_REG: string;
 
 
 
 
 
 
 
  attribute ASYNC_REG of RW_RADDR_S0   : signal is "true";
 
 
 
  attribute ASYNC_REG of RW_RADDR_S1   : signal is "true";
 
 
 
  attribute ASYNC_REG of RW_RSTW_E_S0  : signal is "true";
 
 
 
  attribute ASYNC_REG of RW_RSTW_E_S1  : signal is "true";
 
 
 
  attribute ASYNC_REG of RW_RSTR_S0    : signal is "true";
 
 
 
  attribute ASYNC_REG of RW_RSTR_S1    : signal is "true";
 
 
 
 
 
 
 
  attribute ASYNC_REG of RR_WADDR_S0   : signal is "true";
 
 
 
  attribute ASYNC_REG of RR_WADDR_S1   : signal is "true";
 
 
 
  attribute ASYNC_REG of RR_RSTR_E_S0  : signal is "true";
 
 
 
  attribute ASYNC_REG of RR_RSTR_E_S1  : signal is "true";
 
 
 
  attribute ASYNC_REG of RR_RSTW_S0    : signal is "true";
 
 
 
  attribute ASYNC_REG of RR_RSTW_S1    : signal is "true";
 
 
 
 
 
begin
 
begin
 
 
 
 
 
  RAM : ram_1swar_1ar_gen               -- dual ported memory
 
  RAM : ram_1swar_1ar_gen               -- dual ported memory
 
    generic map (
 
    generic map (
 
      AWIDTH => AWIDTH,
 
      AWIDTH => AWIDTH,
Line 169... Line 155... 
      DATA  => RADDR
 
      DATA  => RADDR
 
    );
 
    );
 
 
 
 
 
  G2B_WW : gray2bin_gen                 -- gray->bin for waddr on write side
 
  G2B_WW : gray2bin_gen                 -- gray->bin for waddr on write side
 
    generic map (DWIDTH => AWIDTH)
 
    generic map (DWIDTH => AWIDTH)
 
    port map (DI => WADDR, DO => WADDR_BIN);
 
    port map (DI => WADDR, DO => WADDR_BIN_W);
 
  G2B_WR : gray2bin_gen                 -- gray->bin for waddr on read  side
 
  G2B_WR : gray2bin_gen                 -- gray->bin for waddr on read  side
 
    generic map (DWIDTH => AWIDTH)
 
    generic map (DWIDTH => AWIDTH)
 
    port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
 
    port map (DI => RR_WADDR_S1, DO => WADDR_BIN_R);
 
  G2B_RW : gray2bin_gen                 -- gray->bin for raddr on write side
 
 
 
    generic map (DWIDTH => AWIDTH)
 
 
 
    port map (DI => RADDR, DO => RADDR_BIN);
 
 
 
  G2B_RR : gray2bin_gen                 -- gray->bin for raddr on read  side
 
  G2B_RR : gray2bin_gen                 -- gray->bin for raddr on read  side
 
    generic map (DWIDTH => AWIDTH)
 
    generic map (DWIDTH => AWIDTH)
 
    port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
 
    port map (DI => RADDR, DO => RADDR_BIN_R);
 
 
 
  G2B_RW : gray2bin_gen                 -- gray->bin for raddr on write side
 
 
 
    generic map (DWIDTH => AWIDTH)
 
 
 
    port map (DI => RW_RADDR_S1, DO => RADDR_BIN_W);
 
 
 
 
 
 
 
  --
 
 
 
  -- write side --------------------------------------------------------------
 
 
 
  --
 
  proc_regw: process (CLKW)
 
  proc_regw: process (CLKW)
 
  begin
 
  begin
 
    if rising_edge(CLKW) then
 
    if rising_edge(CLKW) then
 
      R_REGW <= N_REGW;
 
      RW_RADDR_S0  <= RADDR;            -- sync 0: CLKR->CLKW
 
 
 
      RW_RADDR_S1  <= RW_RADDR_S0;      -- sync 1: CLKW
 
 
 
      RW_SIZEW     <= NW_SIZEW;
 
 
 
      RW_BUSY      <= NW_BUSY;
 
 
 
      RW_RSTW      <= NW_RSTW;
 
 
 
      RW_RSTW_E_S0 <= RR_RSTW_S1;       -- sync 0: CLKR->CLKW
 
 
 
      RW_RSTW_E_S1 <= RW_RSTW_E_S0;     -- sync 1: CLKW
 
 
 
      RW_RSTR_S0   <= RR_RSTR;          -- sync 0: CLKR->CLKW
 
 
 
      RW_RSTR_S1   <= RW_RSTR_S0;       -- sync 1: CLKW
 
    end if;
 
    end if;
 
  end process proc_regw;
 
  end process proc_regw;
 
 
 
 
 
  proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
 
  proc_nextw: process (RW_BUSY, RW_SIZEW, RW_RSTW, RW_RSTW_E_S1, RW_RSTR_S1,
 
                       RADDR, RADDR_S_BIN, WADDR_BIN)
 
                       ENA, RESETW, RADDR_BIN_W, WADDR_BIN_W)
 
 
 
 
 
    variable r : regw_type := regw_init;
 
 
 
    variable n : regw_type := regw_init;
 
 
 
    variable ibusy : slbit := '0';
 
    variable ibusy : slbit := '0';
 
 
 
    variable irstw : slbit := '0';
 
    variable igcw_ce  : slbit := '0';
 
    variable igcw_ce  : slbit := '0';
 
    variable igcw_rst : slbit := '0';
 
    variable igcw_rst : slbit := '0';
 
    variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
 
    variable isizew : slv(a_range) := (others=>'0');
 
  begin
 
  begin
 
 
 
 
 
    r := R_REGW;
 
    isizew := slv(unsigned(RADDR_BIN_W) + unsigned(not WADDR_BIN_W));
 
    n := R_REGW;
 
 
 
 
 
 
 
    isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
 
 
 
    ibusy  := '0';
 
    ibusy  := '0';
 
    igcw_ce  := '0';
 
    igcw_ce  := '0';
 
    igcw_rst := '0';
 
    igcw_rst := '0';
 
 
 
 
 
    if unsigned(isizew) = 0 then        -- if no free slots
 
    if unsigned(isizew) = 0 then        -- if no free slots
 
      ibusy := '1';                       -- next cycle busy=1
 
      ibusy := '1';                       -- next cycle busy=1
 
    end if;
 
    end if;
 
 
 
 
 
    if ENA='1' and r.busy='0' then      -- if ena=1 and this cycle busy=0
 
    if ENA='1' and RW_BUSY='0' then     -- if ena=1 and this cycle busy=0
 
      igcw_ce := '1';                     -- write this value
 
      igcw_ce := '1';                     -- write this value
 
      if unsigned(isizew) = 1 then        -- if this last free slot
 
      if unsigned(isizew) = 1 then        -- if this last free slot
 
        ibusy := '1';                       -- next cycle busy=1
 
        ibusy := '1';                       -- next cycle busy=1
 
      end if;
 
      end if;
 
    end if;
 
    end if;
 
 
 
 
 
 
 
    irstw := RW_RSTW;
 
    if RESETW = '1' then                -- reset(write side) request
 
    if RESETW = '1' then                -- reset(write side) request
 
      n.rstw := '1';                      -- set RSTW flag
 
      irstw := '1';                       -- set RSTW flag
 
    elsif r.rstw_ss = '1' then          -- request gone and return seen
 
    elsif RW_RSTW_E_S1 = '1' then       -- request gone and return seen
 
      n.rstw := '0';                      -- clear RSTW flag
 
      irstw := '0';                       -- clear RSTW flag
 
    end if;
 
    end if;
 
 
 
 
 
    if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
 
    if RW_RSTW='1' and RW_RSTW_E_S1='1' then -- RSTW seen on write and read side
 
      igcw_rst := '1';                     -- clear write address counter
 
      igcw_rst := '1';                     -- clear write address counter
 
    end if;
 
    end if;
 
    if r.rstr_s = '1' then              -- RSTR active
 
    if RW_RSTR_S1 = '1' then            -- RSTR active
 
      igcw_rst := '1';                    -- clear write address counter
 
      igcw_rst := '1';                    -- clear write address counter
 
    end if;
 
    end if;
 
 
 
 
 
    if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
 
    if RESETW='1' or RW_RSTW='1' or RW_RSTW_E_S1='1' or RW_RSTR_S1='1'
 
    then             -- RESETW or RESETR active
 
    then             -- RESETW or RESETR active
 
      ibusy  := '1';                      -- signal write side busy
 
      ibusy  := '1';                      -- signal write side busy
 
      isizew := (others=>'1');
 
      isizew := (others=>'1');
 
    end if;
 
    end if;
 
 
 
 
 
    n.busy  := ibusy;
 
    NW_BUSY  <= ibusy;
 
    n.sizew := isizew;
 
    NW_RSTW  <= irstw;
 
 
 
    NW_SIZEW <= isizew;
 
    n.raddr_c := RADDR;                 -- data captuture from CLKR
 
 
 
    n.raddr_s := r.raddr_c;
 
 
 
    n.rstw_sc := R_REGR.rstw_s;
 
 
 
    n.rstw_ss := r.rstw_sc;
 
 
 
    n.rstr_c  := R_REGR.rstr;
 
 
 
    n.rstr_s  := r.rstr_c;
 
 
 
 
 
 
 
    N_REGW  <= n;
 
 
 
 
 
 
 
    GCW_CE  <= igcw_ce;
 
    GCW_CE  <= igcw_ce;
 
    GCW_RST <= igcw_rst;
 
    GCW_RST <= igcw_rst;
 
    BUSY    <= r.busy;
 
    BUSY    <= RW_BUSY;
 
    SIZEW   <= r.sizew;
 
    SIZEW   <= RW_SIZEW;
 
 
 
 
 
  end process proc_nextw;
 
  end process proc_nextw;
 
 
 
 
 
 
 
  --
 
 
 
  -- read side ---------------------------------------------------------------
 
 
 
  --
 
  proc_regr: process (CLKR)
 
  proc_regr: process (CLKR)
 
  begin
 
  begin
 
    if rising_edge(CLKR) then
 
    if rising_edge(CLKR) then
 
      R_REGR <= N_REGR;
 
      RR_WADDR_S0  <= WADDR;            -- sync 0: CLKW->CLKR
 
 
 
      RR_WADDR_S1  <= RR_WADDR_S0;      -- sync 1: CLKW
 
 
 
      RR_SIZER     <= NR_SIZER;
 
 
 
      RR_VAL       <= NR_VAL;
 
 
 
      RR_RSTR      <= NR_RSTR;
 
 
 
      RR_RSTR_E_S0 <= RW_RSTR_S1;       -- sync 0: CLKW->CLKR
 
 
 
      RR_RSTR_E_S1 <= RR_RSTR_E_S0;     -- sync 1: CLKW
 
 
 
      RR_RSTW_S0   <= RW_RSTW;          -- sync 0: CLKW->CLKR
 
 
 
      RR_RSTW_S1   <= RR_RSTW_S0;       -- sync 1: CLKW
 
    end if;
 
    end if;
 
  end process proc_regr;
 
  end process proc_regr;
 
 
 
 
 
  proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
 
  proc_nextr: process (RR_VAL, RR_SIZER, RR_RSTR, RR_RSTR_E_S1, RR_RSTW_S1,
 
                       WADDR, WADDR_S_BIN, RADDR_BIN)
 
                       HOLD, RESETR, RADDR_BIN_R, WADDR_BIN_R)
 
 
 
 
 
    variable r : regr_type := regr_init;
 
 
 
    variable n : regr_type := regr_init;
 
 
 
    variable ival : slbit := '0';
 
    variable ival : slbit := '0';
 
 
 
    variable irstr : slbit := '0';
 
    variable igcr_ce  : slbit := '0';
 
    variable igcr_ce  : slbit := '0';
 
    variable igcr_rst : slbit := '0';
 
    variable igcr_rst : slbit := '0';
 
    variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
 
    variable isizer : slv(a_range) := (others=>'0');
 
 
 
 
 
  begin
 
  begin
 
 
 
 
 
    r := R_REGR;
 
    isizer := slv(unsigned(WADDR_BIN_R) - unsigned(RADDR_BIN_R));
 
    n := R_REGR;
 
 
 
 
 
 
 
    isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
 
 
 
    ival  := '1';
 
    ival  := '1';
 
    igcr_ce  := '0';
 
    igcr_ce  := '0';
 
    igcr_rst := '0';
 
    igcr_rst := '0';
 
 
 
 
 
    if unsigned(isizer) = 0 then        -- if nothing to read
 
    if unsigned(isizer) = 0 then        -- if nothing to read
 
      ival := '0';                        -- next cycle val=0
 
      ival := '0';                        -- next cycle val=0
 
    end if;
 
    end if;
 
 
 
 
 
    if r.val='1' and HOLD='0' then      -- this cycle val=1 and no hold
 
    if RR_VAL='1' and HOLD='0' then     -- this cycle val=1 and no hold
 
      igcr_ce := '1';                     -- retire this value
 
      igcr_ce := '1';                     -- retire this value
 
      if unsigned(isizer) = 1  then       -- if this is last one
 
      if unsigned(isizer) = 1  then       -- if this is last one
 
        ival := '0';                        -- next cycle val=0
 
        ival := '0';                        -- next cycle val=0
 
      end if;
 
      end if;
 
    end if;
 
    end if;
 
 
 
 
 
 
 
    irstr := RR_RSTR;
 
    if RESETR = '1' then                -- reset(read side) request
 
    if RESETR = '1' then                -- reset(read side) request
 
      n.rstr := '1';                      -- set RSTR flag
 
      irstr := '1';                       -- set RSTR flag
 
    elsif r.rstr_ss = '1' then          -- request gone and return seen
 
    elsif RR_RSTR_E_S1 = '1' then       -- request gone and return seen
 
      n.rstr := '0';                      -- clear RSTR flag
 
      irstr := '0';                       -- clear RSTR flag
 
    end if;
 
    end if;
 
 
 
 
 
    if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
 
    if RR_RSTR='1' and RR_RSTR_E_S1='1' then -- RSTR seen on read and write side
 
      igcr_rst := '1';                     -- clear read address counter
 
      igcr_rst := '1';                     -- clear read address counter
 
    end if;
 
    end if;
 
    if r.rstw_s = '1' then              -- RSTW active
 
    if RR_RSTW_S1 = '1' then            -- RSTW active
 
      igcr_rst := '1';                    -- clear read address counter
 
      igcr_rst := '1';                    -- clear read address counter
 
    end if;
 
    end if;
 
 
 
 
 
    if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
 
    if RESETR='1' or RR_RSTR='1' or RR_RSTR_E_S1='1' or RR_RSTW_S1='1'
 
    then                                -- RESETR or RESETW active 
    then                                -- RESETR or RESETW active 
      ival   := '0';                       -- signal read side empty
 
      ival   := '0';                       -- signal read side empty
 
      isizer := (others=>'0');
 
      isizer := (others=>'0');
 
    end if;
 
    end if;
 
 
 
 
 
    n.val   := ival;
 
    NR_VAL   <= ival;
 
    n.sizer := isizer;
 
    NR_RSTR  <= irstr;
 
 
 
    NR_SIZER <= isizer;
 
    n.waddr_c := WADDR;                 -- data captuture from CLKW
 
 
 
    n.waddr_s := r.waddr_c;
 
 
 
    n.rstr_sc := R_REGW.rstr_s;
 
 
 
    n.rstr_ss := r.rstr_sc;
 
 
 
    n.rstw_c  := R_REGW.rstw;
 
 
 
    n.rstw_s  := r.rstw_c;
 
 
 
 
 
 
 
    N_REGR <= n;
 
 
 
 
 
 
 
    GCR_CE  <= igcr_ce;
 
    GCR_CE  <= igcr_ce;
 
    GCR_RST <= igcr_rst;
 
    GCR_RST <= igcr_rst;
 
    VAL     <= r.val;
 
    VAL     <= RR_VAL;
 
    SIZER   <= r.sizer;
 
    SIZER   <= RR_SIZER;
 
 
 
 
 
  end process proc_nextr;
 
  end process proc_nextr;
 
 
 
 
 
end syn;
 
end syn;
 
 
 
 
 
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