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-- $Id: ram_2swsr_wfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ram_2swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
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--
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--
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-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- force in XST a synthesis as block RAM.
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-- force in XST a synthesis as block RAM.
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-08 422 1.0.4 now numeric_std clean
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-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
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-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
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-- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned();
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-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
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-- 2008-03-02 122 1.0.1 change generic default for BRAM models
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-- 2008-03-02 122 1.0.1 change generic default for BRAM models
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-- 2007-06-03 45 1.0 Initial version
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
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entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
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generic (
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generic (
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signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
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signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
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begin
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begin
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proc_clka: process (CLKA)
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proc_clka: process (CLKA)
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begin
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begin
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if CLKA'event and CLKA='1' then
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if rising_edge(CLKA) then
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if ENA = '1' then
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if ENA = '1' then
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if WEA = '1' then
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if WEA = '1' then
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sv_ram(conv_integer(unsigned(ADDRA))) := DIA;
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sv_ram(to_integer(unsigned(ADDRA))) := DIA;
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end if;
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end if;
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R_DOA <= sv_ram(conv_integer(unsigned(ADDRA)));
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R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
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end if;
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end if;
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end if;
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end if;
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end process proc_clka;
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end process proc_clka;
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proc_clkb: process (CLKB)
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proc_clkb: process (CLKB)
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begin
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begin
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if CLKB'event and CLKB='1' then
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if rising_edge(CLKB) then
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if ENB = '1' then
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if ENB = '1' then
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if WEB = '1' then
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if WEB = '1' then
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sv_ram(conv_integer(unsigned(ADDRB))) := DIB;
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sv_ram(to_integer(unsigned(ADDRB))) := DIB;
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end if;
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end if;
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R_DOB <= sv_ram(conv_integer(unsigned(ADDRB)));
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R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
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end if;
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end if;
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end if;
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end if;
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end process proc_clkb;
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end process proc_clkb;
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DOA <= R_DOA;
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DOA <= R_DOA;
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