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-- $Id: rb_mon.vhd 444 2011-12-25 10:04:58Z mueller $
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-- $Id: rb_mon.vhd 599 2014-10-25 13:43:56Z mueller $
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--
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Module Name: rb_mon - sim
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-- Module Name: rb_mon - sim
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-- Description: rbus monitor (for tb's)
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-- Description: rbus monitor (for tb's)
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2014-10-25 599 4.1.1 use writeoptint()
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-- 2014-09-03 591 4.1 add burst counter; add state checker
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-- 2014-08-30 589 4.0 use hex for addr; 4 bit STAT; monitor ACK=0
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
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-- 2011-12-23 444 3.1 CLK_CYCLE now integer
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-- 2011-12-23 444 3.1 CLK_CYCLE now integer
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-- 2011-11-19 427 3.0.1 now numeric_std clean
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-- 2011-11-19 427 3.0.1 now numeric_std clean
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-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
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-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon
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-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
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-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon
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-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
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-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext)
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CLK_CYCLE : in integer := 0; -- clock cycle number
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CLK_CYCLE : in integer := 0; -- clock cycle number
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ENA : in slbit := '1'; -- enable monitor output
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ENA : in slbit := '1'; -- enable monitor output
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_SRES : in rb_sres_type; -- rbus: response
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
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RB_STAT : in slv3 -- rbus: status flags
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RB_STAT : in slv4 -- rbus: status flags
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);
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);
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end rb_mon;
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end rb_mon;
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architecture sim of rb_mon is
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architecture sim of rb_mon is
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begin
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begin
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proc_moni: process
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proc_moni: process
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variable oline : line;
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variable oline : line;
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variable nhold : integer := 0;
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variable nhold : integer := 0;
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variable nburst : integer := 0;
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variable data : slv16 := (others=>'0');
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variable data : slv16 := (others=>'0');
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variable tag : string(1 to 8) := (others=>' ');
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variable tag : string(1 to 8) := (others=>' ');
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variable err : slbit := '0';
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variable err : slbit := '0';
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variable r_sel : slbit := '0';
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procedure write_data(L: inout line;
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procedure write_data(L: inout line;
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tag: in string;
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tag: in string;
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data: in slv16;
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data: in slv16;
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nhold: in integer := 0;
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nhold: in integer := 0;
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nburst: in integer := 0;
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cond: in boolean := false;
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cond: in boolean := false;
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ctxt: in string := " ") is
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ctxt: in string := " ") is
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begin
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begin
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writetimestamp(L, CLK_CYCLE, tag);
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writetimestamp(L, CLK_CYCLE, tag);
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write(L, RB_MREQ.addr, right, 10);
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writehex(L, RB_MREQ.addr, right, 4);
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write(L, string'(" "));
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write(L, string'(" "));
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writegen(L, data, right, 0, DBASE);
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writegen(L, data, right, 0, DBASE);
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write(L, string'(" "));
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write(L, RB_STAT, right, 4);
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write(L, RB_STAT, right, 4);
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if nhold > 0 then
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writeoptint(L, " hold=", nhold, 2);
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write(L, string'(" nhold="));
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writeoptint(L, " b=", nburst, 2);
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write(L, nhold);
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end if;
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if cond then
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if cond then
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write(L, ctxt);
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write(L, ctxt);
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end if;
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end if;
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writeline(output, L);
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writeline(output, L);
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end procedure write_data;
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end procedure write_data;
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wait until ENA='1'; -- stall process till enabled
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wait until ENA='1'; -- stall process till enabled
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end if;
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end if;
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wait until rising_edge(CLK); -- check at end of clock cycle
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wait until rising_edge(CLK); -- check at end of clock cycle
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if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then
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if RB_MREQ.aval='1' and r_sel='0' then
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nburst := 0;
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end if;
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if RB_MREQ.re='1' or RB_MREQ.we='1' then
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if RB_SRES.err = '1' then
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if RB_SRES.err = '1' then
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err := '1';
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err := '1';
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end if;
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end if;
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if RB_SRES.busy = '1' then
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if RB_SRES.busy = '1' then
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nhold := nhold + 1;
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nhold := nhold + 1;
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if RB_MREQ.we = '1' then
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if RB_MREQ.we = '1' then
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data := RB_MREQ.din;
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data := RB_MREQ.din;
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tag := ": rbwe ";
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tag := ": rbwe ";
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end if;
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end if;
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write_data(oline, tag, data, nhold, err='1', " ERR='1'");
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if RB_SRES.ack = '1' then
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write_data(oline, tag, data, nhold, nburst, err='1', " ERR='1'");
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else
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write_data(oline, tag, data, nhold, nburst, true, " ACK='0'");
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end if;
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nburst := nburst + 1;
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nhold := 0;
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nhold := 0;
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end if;
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end if;
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else
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else
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if nhold > 0 then
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if nhold > 0 then
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write_data(oline, tag, data, nhold, true, " TIMEOUT");
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write_data(oline, tag, data, nhold, nburst, true, " TIMEOUT");
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end if;
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end if;
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nhold := 0;
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nhold := 0;
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err := '0';
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err := '0';
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end if;
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end if;
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if RB_MREQ.init = '1' then -- init
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if RB_MREQ.init = '1' then -- init
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if RB_MREQ.we = '1' then
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write_data(oline, ": rbini ", RB_MREQ.din);
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write_data(oline, ": rbini ", RB_MREQ.din); -- external
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else
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write_data(oline, ": rbint ", RB_MREQ.din); -- internal
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end if;
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end if;
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end if;
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if unsigned(RB_LAM) /= 0 then
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if unsigned(RB_LAM) /= 0 then
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write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active");
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write_data(oline, ": rblam ", RB_LAM, 0, 0, true, " RB_LAM active");
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end if;
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end if;
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r_sel := RB_MREQ.aval;
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end loop;
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end loop;
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end process proc_moni;
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end process proc_moni;
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proc_check: process (CLK)
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variable r_sel : slbit := '0';
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variable r_addr : slv16 := (others=>'0');
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variable idump : boolean := false;
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variable oline : line;
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begin
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if rising_edge(CLK) then
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idump := false;
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-- check that addr doesn't change after 1st aval cycle
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if r_sel='1' and RB_MREQ.addr /= r_addr then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: addr changed after aval; initial addr=");
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writehex(oline, r_addr, right, 4);
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writeline(output, oline);
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idump := true;
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end if;
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-- check that we,re don't come together in core select time
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-- (aval and r_sel) and not at all outside
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if RB_MREQ.aval='1' and r_sel='1' then
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if RB_MREQ.we='1' and RB_MREQ.re='1' then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: we and re both active");
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writeline(output, oline);
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idump := true;
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end if;
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if RB_MREQ.init='1' then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: init seen inside select");
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writeline(output, oline);
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idump := true;
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end if;
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else
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if RB_MREQ.we='1' or RB_MREQ.re='1' then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: no select and we,re seen");
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writeline(output, oline);
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idump := true;
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end if;
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end if;
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-- check that init not seen when aval or select is active
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if RB_MREQ.aval='1' or r_sel='1' then
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if RB_MREQ.init='1' then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: init seen inside aval or select");
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writeline(output, oline);
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idump := true;
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end if;
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end if;
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-- check that SRES isn't touched unless aval or select is active
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if RB_MREQ.aval='0' and r_sel='0' then
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if RB_SRES.dout/=x"0000" or RB_SRES.busy='1' or
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RB_SRES.ack='1' or RB_SRES.err='1' then
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writetimestamp(oline, CLK_CYCLE,
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": FAIL rb_mon: SRES driven outside aval or select");
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writeline(output, oline);
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idump := true;
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end if;
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end if;
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-- dump rbus state in case of any error seen above
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if idump then
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write(oline, string'(" FAIL: MREQ aval="));
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write(oline, RB_MREQ.aval, right, 1);
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write(oline, string'(" re="));
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write(oline, RB_MREQ.re , right, 1);
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write(oline, string'(" we="));
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write(oline, RB_MREQ.we , right, 1);
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write(oline, string'(" init="));
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write(oline, RB_MREQ.init, right, 1);
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write(oline, string'(" sel="));
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write(oline, r_sel , right, 1);
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write(oline, string'(" addr="));
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writehex(oline, RB_MREQ.addr, right, 4);
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write(oline, string'(" din="));
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writehex(oline, RB_MREQ.din, right, 4);
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writeline(output, oline);
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write(oline, string'(" FAIL: SRES ack="));
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write(oline, RB_SRES.ack , right, 1);
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write(oline, string'(" busy="));
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write(oline, RB_SRES.busy, right, 1);
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write(oline, string'(" err="));
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write(oline, RB_SRES.err , right, 1);
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write(oline, string'(" dout="));
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writehex(oline, RB_SRES.dout, right, 4);
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writeline(output, oline);
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end if;
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-- keep track of select state and latch current addr
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if RB_MREQ.aval='1' and r_sel='0' then -- if 1st cycle of aval
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r_addr := RB_MREQ.addr; -- latch addr
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end if;
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-- select simply aval if last cycle (assume all addr are valid)
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r_sel := RB_MREQ.aval;
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end if;
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end process proc_check;
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end sim;
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end sim;
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No newline at end of file
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No newline at end of file
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