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-- $Id: rb_sel.vhd 641 2015-02-01 22:12:15Z mueller $
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-- $Id: rb_sel.vhd 758 2016-04-02 18:01:39Z mueller $
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--
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--
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-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: rbus: address select logic
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-- Description: rbus: address select logic
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31
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-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2016-04-02 758 4.1 streamline code
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-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
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-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
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-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel)
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-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel)
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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assert SAWIDTH<=15 -- at most 32k word devices
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assert SAWIDTH<=15 -- at most 32k word devices
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report "assert(SAWIDTH<=15)" severity failure;
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report "assert(SAWIDTH<=15)" severity failure;
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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variable isel : slbit := '0';
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begin
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begin
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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isel := '0';
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if RB_MREQ.aval='1' and
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if RB_MREQ.aval='1' and
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RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then
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RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then
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isel := '1';
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R_SEL <= '1';
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else
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R_SEL <= '0';
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end if;
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end if;
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R_SEL <= isel;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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SEL <= R_SEL;
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SEL <= R_SEL;
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