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-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: rbd_bram.vhd 593 2014-09-14 22:21:33Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Dependencies: memlib/ram_1swsr_wfirst_gen
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-- Dependencies: memlib/ram_1swsr_wfirst_gen
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--
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--
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-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
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-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
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-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0
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-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
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-- 2011-11-19 427 1.0.3 now numeric_std clean
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-- 2011-11-19 427 1.0.3 now numeric_std clean
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-- 2010-12-31 352 1.0.2 simplify irb_ack logic
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-- 2010-12-31 352 1.0.2 simplify irb_ack logic
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-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
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-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
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-- 2010-12-26 349 1.0 Initial version
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-- 2010-12-26 349 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- rbus registers:
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-- rbus registers:
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--
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--
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-- Address Bits Name r/w/f Function
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-- Addr Bits Name r/w/f Function
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-- bbbbbbb0 cntl r/w/- Control register
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-- 0 cntl r/w/- Control register
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-- 15:10 nbusy r/w/- busy cycles
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-- 15:10 nbusy r/w/- busy cycles
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-- 9:00 addr r/w/- bram address (will auto-increment)
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-- 9:00 addr r/w/- bram address (will auto-increment)
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-- bbbbbbb1 15:00 data r/w/- Data register (read/write to bram via addr)
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-- 1 15:00 data r/w/- Data register (read/write to bram via addr)
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_bram is -- rbus dev: rbus bram test target
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entity rbd_bram is -- rbus dev: rbus bram test target
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-- complete rrirp_aif interface
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-- complete rrirp_aif interface
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generic (
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generic (
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RB_ADDR : slv8 := slv(to_unsigned(2#11110100#,8)));
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RB_ADDR : slv16 := (others=>'0'));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type -- rbus: response
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RB_SRES : out rb_sres_type -- rbus: response
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ibramen := '0';
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ibramen := '0';
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ibramwe := '0';
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ibramwe := '0';
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-- rbus address decoder
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-- rbus address decoder
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n.rbsel := '0';
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n.rbsel := '0';
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if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 1)=RB_ADDR(7 downto 1) then
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if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 1)=RB_ADDR(15 downto 1) then
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n.rbsel := '1';
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n.rbsel := '1';
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ibramen := '1';
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ibramen := '1';
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if irbena = '0' then -- addr valid and selected, but no req
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if irbena = '0' then -- addr valid and selected, but no req
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