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-- $Id: rbd_eyemon.vhd 406 2011-08-14 21:06:44Z mueller $
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-- $Id: rbd_eyemon.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Dependencies: memlib/ram_2swsr_wfirst_gen
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-- Dependencies: memlib/ram_2swsr_wfirst_gen
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--
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--
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-- Test bench: -
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-- Test bench: -
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7
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-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7
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-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9
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-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.3 now numeric_std clean
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-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
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-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
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-- 2010-12-31 352 1.0.1 simplify irb_ack logic
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-- 2010-12-31 352 1.0.1 simplify irb_ack logic
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-- 2010-12-27 349 1.0 Initial version
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-- 2010-12-27 349 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- word 0 counter lsb's
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-- word 0 counter lsb's
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_eyemon is -- rbus dev: eye monitor for serport's
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entity rbd_eyemon is -- rbus dev: eye monitor for serport's
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generic (
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generic (
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RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8);
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RB_ADDR : slv8 := slv(to_unsigned(2#11111000#,8));
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RDIV : slv8 := conv_std_logic_vector(0,8));
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RDIV : slv8 := slv(to_unsigned(0,8)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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DOB => open
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DOB => open
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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n.rdivcnt := r.rdiv;
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n.rdivcnt := r.rdiv;
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if unsigned(r.laddr) /= (2**r.laddr'length)-1 then
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if unsigned(r.laddr) /= (2**r.laddr'length)-1 then
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laddr_inc := '1';
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laddr_inc := '1';
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end if;
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end if;
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else
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else
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n.rdivcnt := unsigned(r.rdivcnt) - 1;
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n.rdivcnt := slv(unsigned(r.rdivcnt) - 1);
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end if;
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end if;
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when s_clr => -- s_clr: clear memory ---------------
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when s_clr => -- s_clr: clear memory ---------------
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laddr_inc := '1';
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laddr_inc := '1';
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n.memwe := '1';
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n.memwe := '1';
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if laddr_we = '1' then
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if laddr_we = '1' then
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n.laddr := RB_MREQ.din(addr_rbf_laddr);
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n.laddr := RB_MREQ.din(addr_rbf_laddr);
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elsif laddr_clr = '1' then
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elsif laddr_clr = '1' then
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n.laddr := (others=>'0');
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n.laddr := (others=>'0');
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elsif laddr_inc = '1' then
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elsif laddr_inc = '1' then
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n.laddr := unsigned(r.laddr) + 1;
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n.laddr := slv(unsigned(r.laddr) + 1);
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end if;
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end if;
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n.laddr_1 := r.laddr;
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n.laddr_1 := r.laddr;
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n.rxsd_1 := RXSD;
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n.rxsd_1 := RXSD;
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ibramdi := (others=>'0');
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ibramdi := (others=>'0');
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if r.memclr = '0' then
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if r.memclr = '0' then
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ibramdi := unsigned(BRAM_DOA) + 1;
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ibramdi := slv(unsigned(BRAM_DOA) + 1);
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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BRAM_ENA <= ibramen;
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BRAM_ENA <= ibramen;
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