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-- $Id: rbd_rbmon.vhd 387 2011-07-03 17:24:52Z mueller $
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-- $Id: rbd_rbmon.vhd 427 2011-11-19 21:04:11Z mueller $
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--
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Dependencies: memlib/ram_1swsr_wfirst_gen
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-- Dependencies: memlib/ram_1swsr_wfirst_gen
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--
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--
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-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
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-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 12.1; ghdl 0.29
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
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-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-11-19 427 1.0.3 now numeric_std clean
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-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
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-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
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-- 2010-12-31 352 1.0.1 simplify irb_ack logic
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-- 2010-12-31 352 1.0.1 simplify irb_ack logic
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-- 2010-12-27 349 1.0 Initial version
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-- 2010-12-27 349 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.rblib.all;
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use work.rblib.all;
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entity rbd_rbmon is -- rbus dev: rbus monitor
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entity rbd_rbmon is -- rbus dev: rbus monitor
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generic (
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generic (
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RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8);
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RB_ADDR : slv8 := slv(to_unsigned(2#11111100#,8));
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AWIDTH : positive := 9);
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AWIDTH : positive := 9);
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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DO => BRAM0_DO
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DO => BRAM0_DO
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);
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);
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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if RESET = '1' then
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if RESET = '1' then
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R_REGS <= regs_init;
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R_REGS <= regs_init;
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else
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else
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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when rbaddr_data =>
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when rbaddr_data =>
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if r.go='1' or RB_MREQ.we='1' then
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if r.go='1' or RB_MREQ.we='1' then
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irb_err := '1';
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irb_err := '1';
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end if;
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end if;
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if RB_MREQ.re = '1' then
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if RB_MREQ.re = '1' then
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n.waddr := unsigned(r.waddr) + 1;
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n.waddr := slv(unsigned(r.waddr) + 1);
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if r.waddr = "11" then
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if r.waddr = "11" then
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laddr_inc := '1';
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laddr_inc := '1';
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end if;
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end if;
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end if;
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end if;
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else -- if non-initial cycles
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else -- if non-initial cycles
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if RB_SRES_SUM.err = '1' then -- keep track of err flags
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if RB_SRES_SUM.err = '1' then -- keep track of err flags
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n.rberr := '1';
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n.rberr := '1';
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end if;
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end if;
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if r.rbnbusy /= rbnbusylast then -- and count
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if r.rbnbusy /= rbnbusylast then -- and count
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n.rbnbusy := unsigned(r.rbnbusy) + 1;
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n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
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end if;
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end if;
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end if;
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end if;
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n.rbnak := not RB_SRES_SUM.ack;
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n.rbnak := not RB_SRES_SUM.ack;
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n.rbtout := RB_SRES_SUM.busy;
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n.rbtout := RB_SRES_SUM.busy;
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end if;
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end if;
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if r.rbtake_1 = '1' then -- rbus transaction just ended
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if r.rbtake_1 = '1' then -- rbus transaction just ended
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n.rbndly := (others=>'0'); -- clear delay counter
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n.rbndly := (others=>'0'); -- clear delay counter
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else -- just idle
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else -- just idle
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if r.rbndly /= rbndlylast then -- count cycles
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if r.rbndly /= rbndlylast then -- count cycles
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n.rbndly := unsigned(r.rbndly) + 1;
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n.rbndly := slv(unsigned(r.rbndly) + 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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if laddr_inc = '1' then
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if laddr_inc = '1' then
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n.laddr := unsigned(r.laddr) + 1;
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n.laddr := slv(unsigned(r.laddr) + 1);
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if r.go='1' and r.laddr=laddrlast then
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if r.go='1' and r.laddr=laddrlast then
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n.wrap := '1';
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n.wrap := '1';
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end if;
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end if;
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end if;
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end if;
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