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-- $Id: rlink_core.vhd 718 2015-12-26 15:59:48Z mueller $
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-- $Id: rlink_core.vhd 767 2016-05-26 07:47:51Z mueller $
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--
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--
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-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Test bench: tb/tb_rlink_direct
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-- Test bench: tb/tb_rlink_direct
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-- tb/tb_rlink_serport
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-- tb/tb_rlink_serport
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-- tb/tb_rlink_tba_ttcombo
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-- tb/tb_rlink_tba_ttcombo
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
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--
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--
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-- Synthesized (xst):
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2015-12-26 718 14.7 131013 xc6slx16-2 312 460 16 150 s 7.0 ver 4.1
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-- 2015-12-26 718 14.7 131013 xc6slx16-2 312 460 16 150 s 7.0 ver 4.1
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-- 2014-12-20 614 14.7 131013 xc6slx16-2 310 453 16 146 s 6.8 ver 4.0
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-- 2014-12-20 614 14.7 131013 xc6slx16-2 310 453 16 146 s 6.8 ver 4.0
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-- 2014-08-13 581 14.7 131013 xc6slx16-2 160 230 0 73 s 6.0 ver 3.0
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-- 2014-08-13 581 14.7 131013 xc6slx16-2 160 230 0 73 s 6.0 ver 3.0
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-- 2014-08-13 581 14.7 131013 xc3s1000-4 160 358 0 221 s 8.9 ver 3.0
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-- 2014-08-13 581 14.7 131013 xc3s1000-4 160 358 0 221 s 8.9 ver 3.0
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2016-05-22 787 4.1.2 don't init N_REGS (vivado fix for fsm inference)
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-- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout
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-- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout
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-- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout
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-- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout
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-- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT
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-- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add s_rxaddrl state
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-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add s_rxaddrl state
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-- 2011-11-19 427 3.1.3 now numeric_std clean
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-- 2011-11-19 427 3.1.3 now numeric_std clean
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'0','0', -- anena,atoena
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'0','0', -- anena,atoena
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(others=>'0') -- atoval
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(others=>'0') -- atoval
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);
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);
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signal R_LREGS : lregs_type := lregs_init; -- state registers link FSM
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signal R_LREGS : lregs_type := lregs_init; -- state registers link FSM
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signal N_LREGS : lregs_type := lregs_init; -- next value state regs link FSM
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signal N_LREGS : lregs_type; -- don't init (vivado fix for fsm infer)
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signal R_BREGS : bregs_type := bregs_init; -- state registers bus FSM
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signal R_BREGS : bregs_type := bregs_init; -- state registers bus FSM
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signal N_BREGS : bregs_type := bregs_init; -- next value state regs bus FSM
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signal N_BREGS : bregs_type; -- don't init (vivado fix for fsm infer)
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signal R_CREGS : cregs_type := cregs_init; -- state registers config
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signal R_CREGS : cregs_type := cregs_init; -- state registers config
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signal N_CREGS : cregs_type := cregs_init; -- next value state regs config
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signal N_CREGS : cregs_type := cregs_init; -- next value state regs config
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signal RTBUF_ENB : slbit := '0';
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signal RTBUF_ENB : slbit := '0';
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signal RTBUF_WEA : slbit := '0';
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signal RTBUF_WEA : slbit := '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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when sl_txeop => -- sl_txeop: send eop ----------------
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when sl_txeop => -- sl_txeop: send eop ----------------
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n.state := sl_txeop; -- needed to prevent vivado iSTATE
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ido := c_rlink_dat_eop; -- send eop character
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ido := c_rlink_dat_eop; -- send eop character
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ival := '1';
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ival := '1';
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if RL_HOLD = '0' then -- wait for accept
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if RL_HOLD = '0' then -- wait for accept
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n.moneop := '1'; -- signal on rl_moni
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n.moneop := '1'; -- signal on rl_moni
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n.state := sl_idle; -- next: idle state, wait for sop
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n.state := sl_idle; -- next: idle state, wait for sop
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