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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [vlib/] [rlink/] [rlink_core8.vhd] - Diff between revs 29 and 30

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-- $Id: rlink_core8.vhd 641 2015-02-01 22:12:15Z mueller $
-- $Id: rlink_core8.vhd 666 2015-04-12 21:17:54Z mueller $
--
--
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
--
-- This program is free software; you may redistribute and/or modify it under
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- the terms of the GNU General Public License as published by the Free
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-- 2014-12-05   596 14.7  131013 xc6slx16-2   352  492   24  176 s  7.0 ver 4.0
-- 2014-12-05   596 14.7  131013 xc6slx16-2   352  492   24  176 s  7.0 ver 4.0
-- 2011-12-09   437 13.1    O40d xc3s1000-4   184  403    0  244 s  9.1
-- 2011-12-09   437 13.1    O40d xc3s1000-4   184  403    0  244 s  9.1
--
--
-- Revision History: 
-- Revision History: 
-- Date         Rev Version  Comment
-- Date         Rev Version  Comment
 
-- 2015-04-11   666   4.1    add ESCXON,ESCFILL in signals, for cdata2byte
-- 2014-10-12   596   4.0    now rlink v4 iface, 4 bit STAT
-- 2014-10-12   596   4.0    now rlink v4 iface, 4 bit STAT
-- 2011-12-09   437   1.0    Initial version
-- 2011-12-09   437   1.0    Initial version
------------------------------------------------------------------------------
------------------------------------------------------------------------------
 
 
library ieee;
library ieee;
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    ENAPIN_RBMON : integer := -1);      -- SB_CNTL for rbmon  (-1=none)
    ENAPIN_RBMON : integer := -1);      -- SB_CNTL for rbmon  (-1=none)
  port (
  port (
    CLK  : in slbit;                    -- clock
    CLK  : in slbit;                    -- clock
    CE_INT : in slbit := '0';           -- rlink ato time unit clock enable
    CE_INT : in slbit := '0';           -- rlink ato time unit clock enable
    RESET  : in slbit;                  -- reset
    RESET  : in slbit;                  -- reset
 
    ESCXON : in slbit;                  -- enable xon/xoff escaping
 
    ESCFILL : in slbit;                 -- enable fill escaping
    RLB_DI : in slv8;                   -- rlink 8b: data in
    RLB_DI : in slv8;                   -- rlink 8b: data in
    RLB_ENA : in slbit;                 -- rlink 8b: data enable
    RLB_ENA : in slbit;                 -- rlink 8b: data enable
    RLB_BUSY : out slbit;               -- rlink 8b: data busy
    RLB_BUSY : out slbit;               -- rlink 8b: data busy
    RLB_DO : out slv8;                  -- rlink 8b: data out
    RLB_DO : out slv8;                  -- rlink 8b: data out
    RLB_VAL : out slbit;                -- rlink 8b: data valid
    RLB_VAL : out slbit;                -- rlink 8b: data valid
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-- RL -> RLB converter (DO handling) -------------
-- RL -> RLB converter (DO handling) -------------
  CD2B : cdata2byte                     -- 9bit comma,data -> byte stream
  CD2B : cdata2byte                     -- 9bit comma,data -> byte stream
    port map (
    port map (
      CLK     => CLK,
      CLK     => CLK,
      RESET   => RESET,
      RESET   => RESET,
      ESCXON  => '0',
      ESCXON  => ESCXON,
      ESCFILL => '0',
      ESCFILL => ESCFILL,
      DI      => RL_DO,
      DI      => RL_DO,
      ENA     => RL_VAL,
      ENA     => RL_VAL,
      BUSY    => RL_HOLD,
      BUSY    => RL_HOLD,
      DO      => RLB_DO_L,
      DO      => RLB_DO_L,
      VAL     => RLB_VAL_L,
      VAL     => RLB_VAL_L,

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