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-- $Id: serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: serport_uart_rx.vhd 421 2011-11-07 21:23:50Z mueller $
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--
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--
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-- Copyright 2007-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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-- Description: serial port UART - receiver
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-- Description: serial port UART - receiver
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--
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--
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-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_serport_uart_rxtx
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-- Test bench: tb/tb_serport_uart_rxtx
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-10-22 417 2.0.3 now numeric_std clean
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-- 2009-07-12 233 2.0.2 remove snoopers
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-- 2009-07-12 233 2.0.2 remove snoopers
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-- 2008-03-02 121 2.0.1 comment out snoopers
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-- 2008-03-02 121 2.0.1 comment out snoopers
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-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
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-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
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-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
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-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
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-- (all 1's); aborts bad start bit after 1/2 cell;
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-- (all 1's); aborts bad start bit after 1/2 cell;
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-- 2007-06-30 62 1.0 Initial version
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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-- synthesis translate_off
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use ieee.std_logic_textio.all;
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use std.textio.all;
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-- synthesis translate_on
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use work.slvtypes.all;
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use work.slvtypes.all;
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entity serport_uart_rx is -- serial port uart: receive part
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entity serport_uart_rx is -- serial port uart: receive part
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generic (
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generic (
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end record regs_type;
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end record regs_type;
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constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
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constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
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constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
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constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle,
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s_idle, -- state
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ccntzero,
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ccntzero, -- ccnt
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dcntzero,
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dcntzero, -- dcnt
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(others=>'0'),
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(others=>'0'), -- bcnt
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(others=>'0')
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(others=>'0') -- sreg
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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begin
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proc_regs: process (CLK)
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proc_regs: process (CLK)
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begin
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begin
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if CLK'event and CLK='1' then
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if rising_edge(CLK) then
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R_REGS <= N_REGS;
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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end process proc_regs;
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end if;
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end if;
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if ld_ccnt = '1' then -- implement ccnt
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if ld_ccnt = '1' then -- implement ccnt
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n.ccnt := CLKDIV;
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n.ccnt := CLKDIV;
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else
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else
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n.ccnt := unsigned(r.ccnt) - 1;
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n.ccnt := slv(unsigned(r.ccnt) - 1);
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end if;
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end if;
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if ld_dcnt = '1' then -- implement dcnt
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if ld_dcnt = '1' then -- implement dcnt
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n.dcnt(CDWIDTH downto 1) := (others=>'0');
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n.dcnt(CDWIDTH downto 1) := (others=>'0');
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n.dcnt(0) := RXSD;
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n.dcnt(0) := RXSD;
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else
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else
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if RXSD = '1' then
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if RXSD = '1' then
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n.dcnt := unsigned(r.dcnt) + 1;
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n.dcnt := slv(unsigned(r.dcnt) + 1);
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end if;
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end if;
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end if;
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end if;
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if ld_bcnt = '1' then -- implement bcnt
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if ld_bcnt = '1' then -- implement bcnt
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n.bcnt := (others=>'0');
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n.bcnt := (others=>'0');
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else
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else
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if ce_bcnt = '1' then
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if ce_bcnt = '1' then
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n.bcnt := unsigned(r.bcnt) + 1;
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n.bcnt := slv(unsigned(r.bcnt) + 1);
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end if;
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end if;
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end if;
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end if;
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N_REGS <= n;
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N_REGS <= n;
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