| Line 1... |
Line 1... |
-- $Id: pdp11_cache.vhd 677 2015-05-09 21:52:32Z mueller $
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-- $Id: pdp11_cache.vhd 767 2016-05-26 07:47:51Z mueller $
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--
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--
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-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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-- Software Foundation, either version 2, or at your option any later version.
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--
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--
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| Line 16... |
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-- Description: pdp11: cache
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-- Description: pdp11: cache
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--
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--
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Dependencies: memlib/ram_2swsr_rfirst_gen
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-- Test bench: -
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-- Test bench: -
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
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--
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-- Synthesis results
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-- clw = cache line width (tag+data)
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-- eff = efficiency (fraction of used BRAM colums)
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-- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1
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-- TWIDTH flop lutl lutm RAMB36 RAMB18 bram clw eff
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-- 9 43 106 0 0 5 2.5 45 100%
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-- 8 43 109 0 5 0 5.0 44 97%
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-- 7 43 107 0 10 4 12.0 43 89%
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-- 6 43 106 0 19 4 21.0 42 100%
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-- 5 58! 106 0 41 0 41.0 41 100%
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference)
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-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB)
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-- 2011-11-18 427 1.0.3 now numeric_std clean
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-- 2011-11-18 427 1.0.3 now numeric_std clean
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-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
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-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
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-- factor invariants out of if's; fix tag rmiss logic
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-- factor invariants out of if's; fix tag rmiss logic
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-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
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-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
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-- recode, ghdl doesn't like partial vector port maps
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-- recode, ghdl doesn't like partial vector port maps
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| Line 36... |
Line 50... |
use work.slvtypes.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.memlib.all;
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use work.pdp11.all;
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use work.pdp11.all;
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entity pdp11_cache is -- cache
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entity pdp11_cache is -- cache
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generic (
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TWIDTH : positive := 9); -- tag width (5 to 9)
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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GRESET : in slbit; -- general reset
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GRESET : in slbit; -- general reset
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EM_MREQ : in em_mreq_type; -- em request
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EM_MREQ : in em_mreq_type; -- em request
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EM_SRES : out em_sres_type; -- em response
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EM_SRES : out em_sres_type; -- em response
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| Line 57... |
Line 73... |
end pdp11_cache;
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end pdp11_cache;
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architecture syn of pdp11_cache is
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architecture syn of pdp11_cache is
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constant lwidth: positive := 22-2-TWIDTH; -- line address width
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subtype t_range is integer range TWIDTH-1 downto 0; -- tag value regs
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subtype l_range is integer range lwidth-1 downto 0; -- line addr regs
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subtype af_tag is integer range 22-1 downto 22-TWIDTH; -- tag address
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subtype af_line is integer range 22-TWIDTH-1 downto 2; -- line address
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subtype df_byte3 is integer range 31 downto 24;
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subtype df_byte2 is integer range 23 downto 16;
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subtype df_byte1 is integer range 15 downto 8;
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subtype df_byte0 is integer range 7 downto 0;
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subtype df_word1 is integer range 31 downto 16;
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subtype df_word0 is integer range 15 downto 0;
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type state_type is (
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type state_type is (
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s_idle, -- s_idle: wait for req
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s_idle, -- s_idle: wait for req
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s_read, -- s_read: read cycle
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s_read, -- s_read: read cycle
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s_rmiss, -- s_rmiss: read miss
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s_rmiss, -- s_rmiss: read miss
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s_write -- s_write: write cycle
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s_write -- s_write: write cycle
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);
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);
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type regs_type is record
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type regs_type is record
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state : state_type; -- state
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state : state_type; -- state
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addr_w : slbit; -- address - word select
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addr_w : slbit; -- address - word select
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addr_l : slv11; -- address - cache line address
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addr_l : slv(l_range); -- address - cache line address
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addr_t : slv9; -- address - cache tag part
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addr_t : slv(t_range); -- address - cache tag part
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be : slv4; -- byte enables (at 4 byte level)
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be : slv4; -- byte enables (at 4 byte level)
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di : slv16; -- data
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di : slv16; -- data
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end record regs_type;
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end record regs_type;
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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s_idle, -- state
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s_idle, -- state
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'0', -- addr_w
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'0', -- addr_w
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(others=>'0'), -- addr_l
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slv(to_unsigned(0,lwidth)), -- addr_l
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(others=>'0'), -- addr_t
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slv(to_unsigned(0,TWIDTH)), -- addr_t
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(others=>'0'), -- be
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(others=>'0'), -- be
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(others=>'0') -- di
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(others=>'0') -- di
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);
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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signal CMEM_TAG_CEA : slbit := '0';
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signal CMEM_TAG_CEA : slbit := '0';
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signal CMEM_TAG_CEB : slbit := '0';
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signal CMEM_TAG_CEB : slbit := '0';
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signal CMEM_TAG_WEA : slbit := '0';
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signal CMEM_TAG_WEA : slbit := '0';
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signal CMEM_TAG_WEB : slbit := '0';
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signal CMEM_TAG_WEB : slbit := '0';
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signal CMEM_TAG_DIB : slv9 := (others=>'0');
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signal CMEM_TAG_DIB : slv(t_range) := (others=>'0');
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signal CMEM_TAG_DOA : slv9 := (others=>'0');
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signal CMEM_TAG_DOA : slv(t_range) := (others=>'0');
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signal CMEM_DAT_CEA : slbit := '0';
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signal CMEM_DAT_CEA : slbit := '0';
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signal CMEM_DAT_CEB : slbit := '0';
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signal CMEM_DAT_CEB : slbit := '0';
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signal CMEM_DAT_WEA : slv4 := "0000";
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signal CMEM_DAT_WEA : slv4 := "0000";
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signal CMEM_DAT_WEB : slv4 := "0000";
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signal CMEM_DAT_WEB : slv4 := "0000";
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signal CMEM_DIA_0 : slv9 := (others=>'0');
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signal CMEM_DIA_0 : slv9 := (others=>'0');
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| Line 110... |
Line 142... |
signal CMEM_DOA_2 : slv9 := (others=>'0');
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signal CMEM_DOA_2 : slv9 := (others=>'0');
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signal CMEM_DOA_3 : slv9 := (others=>'0');
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signal CMEM_DOA_3 : slv9 := (others=>'0');
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begin
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begin
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assert TWIDTH>=5 and TWIDTH<=9
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report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH"
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severity failure;
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CMEM_TAG : ram_2swsr_rfirst_gen
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CMEM_TAG : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 11,
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AWIDTH => lwidth,
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DWIDTH => 9)
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DWIDTH => twidth)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_TAG_CEA,
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ENA => CMEM_TAG_CEA,
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ENB => CMEM_TAG_CEB,
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ENB => CMEM_TAG_CEB,
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WEA => CMEM_TAG_WEA,
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WEA => CMEM_TAG_WEA,
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WEB => CMEM_TAG_WEB,
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WEB => CMEM_TAG_WEB,
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ADDRA => EM_MREQ.addr(12 downto 2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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ADDRB => R_REGS.addr_l,
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DIA => EM_MREQ.addr(21 downto 13),
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DIA => EM_MREQ.addr(af_tag),
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DIB => CMEM_TAG_DIB,
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DIB => CMEM_TAG_DIB,
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DOA => CMEM_TAG_DOA,
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DOA => CMEM_TAG_DOA,
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DOB => open
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DOB => open
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);
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);
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CMEM_DAT0 : ram_2swsr_rfirst_gen
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CMEM_DAT0 : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 11,
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AWIDTH => lwidth,
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DWIDTH => 9)
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DWIDTH => 9)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(0),
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WEA => CMEM_DAT_WEA(0),
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WEB => CMEM_DAT_WEB(0),
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WEB => CMEM_DAT_WEB(0),
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ADDRA => EM_MREQ.addr(12 downto 2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_0,
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DIA => CMEM_DIA_0,
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DIB => CMEM_DIB_0,
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DIB => CMEM_DIB_0,
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DOA => CMEM_DOA_0,
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DOA => CMEM_DOA_0,
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DOB => open
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DOB => open
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);
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);
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CMEM_DAT1 : ram_2swsr_rfirst_gen
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CMEM_DAT1 : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 11,
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AWIDTH => lwidth,
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DWIDTH => 9)
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DWIDTH => 9)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(1),
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WEA => CMEM_DAT_WEA(1),
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WEB => CMEM_DAT_WEB(1),
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WEB => CMEM_DAT_WEB(1),
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ADDRA => EM_MREQ.addr(12 downto 2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_1,
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DIA => CMEM_DIA_1,
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DIB => CMEM_DIB_1,
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DIB => CMEM_DIB_1,
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DOA => CMEM_DOA_1,
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DOA => CMEM_DOA_1,
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DOB => open
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DOB => open
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);
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);
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CMEM_DAT2 : ram_2swsr_rfirst_gen
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CMEM_DAT2 : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 11,
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AWIDTH => lwidth,
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DWIDTH => 9)
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DWIDTH => 9)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(2),
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WEA => CMEM_DAT_WEA(2),
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WEB => CMEM_DAT_WEB(2),
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WEB => CMEM_DAT_WEB(2),
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ADDRA => EM_MREQ.addr(12 downto 2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_2,
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DIA => CMEM_DIA_2,
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DIB => CMEM_DIB_2,
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DIB => CMEM_DIB_2,
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DOA => CMEM_DOA_2,
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DOA => CMEM_DOA_2,
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DOB => open
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DOB => open
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);
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);
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|
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CMEM_DAT3 : ram_2swsr_rfirst_gen
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CMEM_DAT3 : ram_2swsr_rfirst_gen
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generic map (
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generic map (
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AWIDTH => 11,
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AWIDTH => lwidth,
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DWIDTH => 9)
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DWIDTH => 9)
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port map (
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port map (
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CLKA => CLK,
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CLKA => CLK,
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CLKB => CLK,
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CLKB => CLK,
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ENA => CMEM_DAT_CEA,
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ENA => CMEM_DAT_CEA,
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ENB => CMEM_DAT_CEB,
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ENB => CMEM_DAT_CEB,
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WEA => CMEM_DAT_WEA(3),
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WEA => CMEM_DAT_WEA(3),
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WEB => CMEM_DAT_WEB(3),
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WEB => CMEM_DAT_WEB(3),
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ADDRA => EM_MREQ.addr(12 downto 2),
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ADDRA => EM_MREQ.addr(af_line),
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ADDRB => R_REGS.addr_l,
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ADDRB => R_REGS.addr_l,
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DIA => CMEM_DIA_3,
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DIA => CMEM_DIA_3,
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DIB => CMEM_DIB_3,
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DIB => CMEM_DIB_3,
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DOA => CMEM_DOA_3,
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DOA => CMEM_DOA_3,
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DOB => open
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DOB => open
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| Line 227... |
Line 263... |
|
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variable r : regs_type := regs_init;
|
variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable n : regs_type := regs_init;
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|
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variable iaddr_w : slbit := '0';
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variable iaddr_w : slbit := '0';
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variable iaddr_l : slv11 := (others=>'0');
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variable iaddr_l : slv(l_range) := (others=>'0');
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variable iaddr_t : slv9 := (others=>'0');
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variable iaddr_t : slv(t_range) := (others=>'0');
|
|
|
variable itagok : slbit := '0';
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variable itagok : slbit := '0';
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variable ivalok : slbit := '0';
|
variable ivalok : slbit := '0';
|
|
|
variable icmem_tag_cea : slbit := '0';
|
variable icmem_tag_cea : slbit := '0';
|
variable icmem_tag_ceb : slbit := '0';
|
variable icmem_tag_ceb : slbit := '0';
|
variable icmem_tag_wea : slbit := '0';
|
variable icmem_tag_wea : slbit := '0';
|
variable icmem_tag_web : slbit := '0';
|
variable icmem_tag_web : slbit := '0';
|
variable icmem_tag_dib : slv9 := (others=>'0');
|
variable icmem_tag_dib : slv(t_range) := (others=>'0');
|
variable icmem_dat_cea : slbit := '0';
|
variable icmem_dat_cea : slbit := '0';
|
variable icmem_dat_ceb : slbit := '0';
|
variable icmem_dat_ceb : slbit := '0';
|
variable icmem_dat_wea : slv4 := "0000";
|
variable icmem_dat_wea : slv4 := "0000";
|
variable icmem_dat_web : slv4 := "0000";
|
variable icmem_dat_web : slv4 := "0000";
|
variable icmem_val_doa : slv4 := "0000";
|
variable icmem_val_doa : slv4 := "0000";
|
| Line 262... |
Line 298... |
|
|
r := R_REGS;
|
r := R_REGS;
|
n := R_REGS;
|
n := R_REGS;
|
|
|
iaddr_w := EM_MREQ.addr(1); -- get word select
|
iaddr_w := EM_MREQ.addr(1); -- get word select
|
iaddr_l := EM_MREQ.addr(12 downto 2); -- get cache line addr
|
iaddr_l := EM_MREQ.addr(af_line); -- get cache line addr
|
iaddr_t := EM_MREQ.addr(21 downto 13); -- get cache tag part
|
iaddr_t := EM_MREQ.addr(af_tag); -- get cache tag part
|
|
|
icmem_tag_cea := '0';
|
icmem_tag_cea := '0';
|
icmem_tag_ceb := '0';
|
icmem_tag_ceb := '0';
|
icmem_tag_wea := '0';
|
icmem_tag_wea := '0';
|
icmem_tag_web := '0';
|
icmem_tag_web := '0';
|
| Line 278... |
Line 314... |
icmem_dat_web := "0000";
|
icmem_dat_web := "0000";
|
icmem_val_dib := "0000";
|
icmem_val_dib := "0000";
|
icmem_dat_dib := MEM_DO; -- default, local define whenver used
|
icmem_dat_dib := MEM_DO; -- default, local define whenver used
|
|
|
icmem_val_doa(0) := CMEM_DOA_0(8);
|
icmem_val_doa(0) := CMEM_DOA_0(8);
|
icmem_dat_doa( 7 downto 0) := CMEM_DOA_0(7 downto 0);
|
icmem_dat_doa(df_byte0) := CMEM_DOA_0(df_byte0);
|
icmem_val_doa(1) := CMEM_DOA_1(8);
|
icmem_val_doa(1) := CMEM_DOA_1(8);
|
icmem_dat_doa(15 downto 8) := CMEM_DOA_1(7 downto 0);
|
icmem_dat_doa(df_byte1) := CMEM_DOA_1(df_byte0);
|
icmem_val_doa(2) := CMEM_DOA_2(8);
|
icmem_val_doa(2) := CMEM_DOA_2(8);
|
icmem_dat_doa(23 downto 16) := CMEM_DOA_2(7 downto 0);
|
icmem_dat_doa(df_byte2) := CMEM_DOA_2(df_byte0);
|
icmem_val_doa(3) := CMEM_DOA_3(8);
|
icmem_val_doa(3) := CMEM_DOA_3(8);
|
icmem_dat_doa(31 downto 24) := CMEM_DOA_3(7 downto 0);
|
icmem_dat_doa(df_byte3) := CMEM_DOA_3(df_byte0);
|
|
|
itagok := '0';
|
itagok := '0';
|
if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
|
if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
|
itagok := '1';
|
itagok := '1';
|
end if;
|
end if;
|
| Line 404... |
Line 440... |
CMEM_DAT_CEB <= icmem_dat_ceb;
|
CMEM_DAT_CEB <= icmem_dat_ceb;
|
CMEM_DAT_WEA <= icmem_dat_wea;
|
CMEM_DAT_WEA <= icmem_dat_wea;
|
CMEM_DAT_WEB <= icmem_dat_web;
|
CMEM_DAT_WEB <= icmem_dat_web;
|
|
|
CMEM_DIA_0(8) <= '1';
|
CMEM_DIA_0(8) <= '1';
|
CMEM_DIA_0(7 downto 0) <= EM_MREQ.din( 7 downto 0);
|
CMEM_DIA_0(df_byte0) <= EM_MREQ.din(df_byte0);
|
CMEM_DIA_1(8) <= '1';
|
CMEM_DIA_1(8) <= '1';
|
CMEM_DIA_1(7 downto 0) <= EM_MREQ.din(15 downto 8);
|
CMEM_DIA_1(df_byte0) <= EM_MREQ.din(df_byte1);
|
CMEM_DIA_2(8) <= '1';
|
CMEM_DIA_2(8) <= '1';
|
CMEM_DIA_2(7 downto 0) <= EM_MREQ.din( 7 downto 0);
|
CMEM_DIA_2(df_byte0) <= EM_MREQ.din(df_byte0);
|
CMEM_DIA_3(8) <= '1';
|
CMEM_DIA_3(8) <= '1';
|
CMEM_DIA_3(7 downto 0) <= EM_MREQ.din(15 downto 8);
|
CMEM_DIA_3(df_byte0) <= EM_MREQ.din(df_byte1);
|
|
|
CMEM_DIB_0(8) <= icmem_val_dib(0);
|
CMEM_DIB_0(8) <= icmem_val_dib(0);
|
CMEM_DIB_0(7 downto 0) <= icmem_dat_dib(7 downto 0);
|
CMEM_DIB_0(df_byte0) <= icmem_dat_dib(df_byte0);
|
CMEM_DIB_1(8) <= icmem_val_dib(1);
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CMEM_DIB_1(8) <= icmem_val_dib(1);
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CMEM_DIB_1(7 downto 0) <= icmem_dat_dib(15 downto 8);
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CMEM_DIB_1(df_byte0) <= icmem_dat_dib(df_byte1);
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CMEM_DIB_2(8) <= icmem_val_dib(2);
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CMEM_DIB_2(8) <= icmem_val_dib(2);
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CMEM_DIB_2(7 downto 0) <= icmem_dat_dib(23 downto 16);
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CMEM_DIB_2(df_byte0) <= icmem_dat_dib(df_byte2);
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CMEM_DIB_3(8) <= icmem_val_dib(3);
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CMEM_DIB_3(8) <= icmem_val_dib(3);
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CMEM_DIB_3(7 downto 0) <= icmem_dat_dib(31 downto 24);
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CMEM_DIB_3(df_byte0) <= icmem_dat_dib(df_byte3);
|
|
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EM_SRES <= em_sres_init;
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EM_SRES <= em_sres_init;
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EM_SRES.ack_r <= iackr;
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EM_SRES.ack_r <= iackr;
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EM_SRES.ack_w <= iackw;
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EM_SRES.ack_w <= iackw;
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case iosel is
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case iosel is
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when "00" => EM_SRES.dout <= icmem_dat_doa(15 downto 0);
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when "00" => EM_SRES.dout <= icmem_dat_doa(df_word0);
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when "01" => EM_SRES.dout <= icmem_dat_doa(31 downto 16);
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when "01" => EM_SRES.dout <= icmem_dat_doa(df_word1);
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when "10" => EM_SRES.dout <= MEM_DO(15 downto 0);
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when "10" => EM_SRES.dout <= MEM_DO(df_word0);
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when "11" => EM_SRES.dout <= MEM_DO(31 downto 16);
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when "11" => EM_SRES.dout <= MEM_DO(df_word1);
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when others => null;
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when others => null;
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end case;
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end case;
|
|
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CHIT <= ichit;
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CHIT <= ichit;
|
|
|
