| Line 1... |
Line 1... |
-- $Id: pdp11_core_rbus.vhd 591 2014-09-06 17:45:38Z mueller $
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-- $Id: pdp11_core_rbus.vhd 621 2014-12-26 21:20:05Z mueller $
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--
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--
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-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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| Line 18... |
Line 18... |
-- Dependencies: -
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-- Dependencies: -
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-- Test bench: tb/tb_rlink_tba_pdp11core
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-- Test bench: tb/tb_rlink_tba_pdp11core
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--
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--
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
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--
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-- Synthesized (xst):
|
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2014-12-21 591 14.7 131013 xc6slx16-2 52 118 0 58 s 4.9
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--
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-- Revision History: -
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-- Revision History: -
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2014-12-26 621 1.4 use full size 4k word ibus window
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-- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr
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-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT
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-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT
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-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
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-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
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-- 2011-11-18 427 1.1.1 now numeric_std clean
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-- 2011-11-18 427 1.1.1 now numeric_std clean
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-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
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-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
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-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
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-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
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| Line 47... |
Line 54... |
-- 2007-07-08 65 1.0 Initial version
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-- 2007-07-08 65 1.0 Initial version
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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--
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-- rbus registers:
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-- rbus registers:
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--
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--
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-- Address Bits Name r/w/i Function
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-- Addr Bits Name r/w/f Function
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--
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--
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-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type)
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-- 00000 conf r/w/- cpu configuration (e.g. cpu type)
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-- (currently unused, all bits MBZ)
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-- (currently unused, all bits MBZ)
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-- bbb00001 cntl -/f/- cpu control
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-- 00001 cntl -/f/- cpu control
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-- 3:0 func function code
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-- 3:00 func function code
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-- 0000: noop
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-- 0000: noop
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-- 0001: start
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-- 0001: start
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-- 0010: stop
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-- 0010: stop
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-- 0011: continue
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-- 0011: continue
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-- 0100: step
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-- 0100: step
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-- 1111: reset (soft)
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-- 1111: reset (soft)
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-- bbb00010 stat r/-/- cpu status
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-- 00010 stat r/-/- cpu status
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-- 7:04 cpurust r/-/- cp_stat: cpurust
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-- 7:04 cpurust r/-/- cp_stat: cpurust
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-- 3 cpuhalt r/-/- cp_stat: cpuhalt
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-- 3 cpuhalt r/-/- cp_stat: cpuhalt
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-- 2 cpugo r/-/- cp_stat: cpugo
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-- 2 cpugo r/-/- cp_stat: cpugo
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-- 1 cmdmerr r/-/- cp_stat: cmdmerr
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-- 1 cmdmerr r/-/- cp_stat: cmdmerr
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-- 0 cmderr r/-/- cp_stat: cmderr
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-- 0 cmderr r/-/- cp_stat: cmderr
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-- bbb00011 psw r/w/- processor status word access
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-- 00011 psw r/w/- processor status word access
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-- bbb00100 al r/w/- address register, low
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-- 00100 al r/w/- address register, low
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-- bbb00101 ah r/w/- address register, high
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-- 00101 ah r/w/- address register, high
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-- 7 ubm r/w/- ubmap access
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-- 7 ubm r/w/- ubmap access
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-- 6 p22 r/w/- 22bit access
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-- 6 p22 r/w/- 22bit access
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-- 5: 0 addr r/w/- addr(21:16)
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-- 5:00 addr r/w/- addr(21:16)
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-- bbb00110 mem r/w/- memory access
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-- 00110 mem r/w/- memory access
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-- bbb00111 memi r/w/- memory access, inc address
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-- 00111 memi r/w/- memory access, inc address
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-- bbb01rrr gpr[] r/w/- general purpose regs
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-- 01rrr gpr[] r/w/- general purpose regs
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-- bbb10000 ibrb r/w/- ibr base address
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-- 10000 membe r/w/- memory write byte enables
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-- 12:06 base r/w/- ibr window base address
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-- 3 stick r/w/- sticky flag
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-- 1:00 we r/w/- byte enables (00 equivalent to 11)
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-- 1:00 be r/w/- byte enables
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-- www----- ibr[] r/w/- ibr window (32 words)
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--
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--
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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| Line 92... |
Line 98... |
|
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-- ----------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------
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|
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entity pdp11_core_rbus is -- core to rbus interface
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entity pdp11_core_rbus is -- core to rbus interface
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generic (
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generic (
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RB_ADDR_CORE : slv16 := slv(to_unsigned(2#0000000000000000#,16));
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RB_ADDR_CORE : slv16 := slv(to_unsigned(16#0000#,16));
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RB_ADDR_IBUS : slv16 := slv(to_unsigned(2#0000000010000000#,16)));
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RB_ADDR_IBUS : slv16 := slv(to_unsigned(16#4000#,16)));
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port (
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port (
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CLK : in slbit; -- clock
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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RB_SRES : out rb_sres_type; -- rbus: response
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| Line 129... |
Line 135... |
cpfunc : slv5; -- cp function
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cpfunc : slv5; -- cp function
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cpugo_1 : slbit; -- prev cycle cpugo
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cpugo_1 : slbit; -- prev cycle cpugo
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addr : slv22_1; -- address register
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addr : slv22_1; -- address register
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ena_22bit : slbit; -- 22bit enable
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ena_22bit : slbit; -- 22bit enable
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ena_ubmap : slbit; -- ubmap enable
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ena_ubmap : slbit; -- ubmap enable
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ibrbase : slv(c_ibrb_ibf_base); -- ibr base address
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membe : slv2; -- memory write byte enables
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ibrbe : slv2; -- ibr byte enables
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membestick : slbit; -- memory write byte enables sticky
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ibrberet : slv2; -- ibr byte enables (for readback)
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doinc : slbit; -- at cmdack: do addr reg inc
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doinc : slbit; -- at cmdack: do addr reg inc
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waitstep : slbit; -- at cmdack: wait for cpu step complete
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waitstep : slbit; -- at cmdack: wait for cpu step complete
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end record regs_type;
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end record regs_type;
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|
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constant regs_init : regs_type := (
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constant regs_init : regs_type := (
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| Line 144... |
Line 149... |
'0', -- cpreq
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'0', -- cpreq
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(others=>'0'), -- cpfunc
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(others=>'0'), -- cpfunc
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'0', -- cpugo_1
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'0', -- cpugo_1
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(others=>'0'), -- addr
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(others=>'0'), -- addr
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'0','0', -- ena_22bit, ena_ubmap
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'0','0', -- ena_22bit, ena_ubmap
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(others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet
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"11",'0', -- membe,membestick
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'0','0' -- doinc, waitstep
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'0','0' -- doinc, waitstep
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);
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);
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|
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signal R_REGS : regs_type := regs_init; -- state registers
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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signal N_REGS : regs_type := regs_init; -- next value state regs
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| Line 210... |
Line 215... |
n.rbselc := '0';
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n.rbselc := '0';
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if RB_MREQ.aval='1' then
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if RB_MREQ.aval='1' then
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if RB_MREQ.addr(15 downto 5)=RB_ADDR_CORE(15 downto 5) then
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if RB_MREQ.addr(15 downto 5)=RB_ADDR_CORE(15 downto 5) then
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n.rbselc := '1';
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n.rbselc := '1';
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end if;
|
end if;
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if RB_MREQ.addr(15 downto 5)=RB_ADDR_IBUS(15 downto 5) then
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if RB_MREQ.addr(15 downto 12)=RB_ADDR_IBUS(15 downto 12) then
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n.rbseli := '1';
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n.rbseli := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
|
if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
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| Line 251... |
Line 256... |
if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
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if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
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n.waitstep := '1';
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n.waitstep := '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
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when c_rbaddr_stat => -- stat -------------------------
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when c_rbaddr_stat => -- stat ------------------
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irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
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irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
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irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
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irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
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irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
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irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
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irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
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irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
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irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
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irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
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|
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when c_rbaddr_psw => -- psw --------------------------
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when c_rbaddr_psw => -- psw -------------------
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if irbena = '1' then
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rpsw;
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n.cpfunc := c_cpfunc_rpsw;
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n.cpfunc(0) := RB_MREQ.we;
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n.cpfunc(0) := RB_MREQ.we;
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icpreq := '1';
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icpreq := '1';
|
end if;
|
end if;
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|
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when c_rbaddr_al => -- al ---------------------------
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when c_rbaddr_al => -- al --------------------
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irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
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irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
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if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
n.addr := (others=>'0'); -- write to al clears ah !!
|
n.addr := (others=>'0'); -- write to al clears ah !!
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n.ena_22bit := '0';
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n.ena_22bit := '0';
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n.ena_ubmap := '0';
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n.ena_ubmap := '0';
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n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
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n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
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end if;
|
end if;
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|
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when c_rbaddr_ah => -- ah ---------------------------
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when c_rbaddr_ah => -- ah --------------------
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irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
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irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
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irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
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irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
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irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
|
irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
|
if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
|
n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
|
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
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n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
|
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
|
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
|
end if;
|
end if;
|
|
|
when c_rbaddr_mem => -- mem -----------------
|
when c_rbaddr_mem => -- mem -------------------
|
if irbena = '1' then
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
icpreq := '1';
|
icpreq := '1';
|
end if;
|
end if;
|
|
|
when c_rbaddr_memi => -- memi ----------------
|
when c_rbaddr_memi => -- memi ------------------
|
if irbena = '1' then
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc := c_cpfunc_rmem;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.doinc := '1';
|
n.doinc := '1';
|
icpreq := '1';
|
icpreq := '1';
|
end if;
|
end if;
|
|
|
when c_rbaddr_r0 | c_rbaddr_r1 |
|
when c_rbaddr_r0 | c_rbaddr_r1 |
|
c_rbaddr_r2 | c_rbaddr_r3 |
|
c_rbaddr_r2 | c_rbaddr_r3 |
|
c_rbaddr_r4 | c_rbaddr_r5 |
|
c_rbaddr_r4 | c_rbaddr_r5 |
|
c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
|
c_rbaddr_sp | c_rbaddr_pc => -- r* -----------------
|
if irbena = '1' then
|
if irbena = '1' then
|
n.cpfunc := c_cpfunc_rreg;
|
n.cpfunc := c_cpfunc_rreg;
|
n.cpfunc(0) := RB_MREQ.we;
|
n.cpfunc(0) := RB_MREQ.we;
|
icpreq := '1';
|
icpreq := '1';
|
end if;
|
end if;
|
|
|
when c_rbaddr_ibrb => -- ibrb ----------------
|
when c_rbaddr_membe => -- membe -----------------
|
irb_dout(c_ibrb_ibf_base) := r.ibrbase;
|
irb_dout(c_membe_rbf_be) := r.membe;
|
irb_dout(c_ibrb_ibf_be) := r.ibrberet;
|
irb_dout(c_membe_rbf_stick) := r.membestick;
|
if RB_MREQ.we = '1' then
|
if RB_MREQ.we = '1' then
|
n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base);
|
n.membe := RB_MREQ.din(c_membe_rbf_be);
|
n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be);
|
n.membestick := RB_MREQ.din(c_membe_rbf_stick);
|
if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ?
|
|
n.ibrbe := "11";
|
|
else -- otherwise take 2 LSB's
|
|
n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be);
|
|
end if;
|
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
irb_ack := '0';
|
irb_ack := '0';
|
|
|
| Line 339... |
Line 339... |
|
|
when s_cpwait => -- s_cpwait: wait for cp port ack ----
|
when s_cpwait => -- s_cpwait: wait for cp port ack ----
|
n.cpreq := '0'; -- cpreq only for 1 cycle
|
n.cpreq := '0'; -- cpreq only for 1 cycle
|
|
|
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
|
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
|
|
if r.cpfunc = c_cpfunc_wmem and -- if wmem command
|
|
r.membestick = '0' then -- and be's not sticky
|
|
n.membe := "11"; -- re-enable both bytes
|
|
end if;
|
n.state := s_idle; -- quit
|
n.state := s_idle; -- quit
|
else
|
else
|
irb_dout := CP_DOUT;
|
irb_dout := CP_DOUT;
|
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
|
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
|
if CP_STAT.cmdack = '1' then -- normal cycle end
|
if CP_STAT.cmdack = '1' then -- normal cycle end
|
|
if r.cpfunc = c_cpfunc_wmem and -- if wmem command
|
|
r.membestick = '0' then -- and be's not sticky
|
|
n.membe := "11"; -- re-enable both bytes
|
|
end if;
|
if r.doinc = '1' then
|
if r.doinc = '1' then
|
n.addr := slv(unsigned(r.addr) + 1);
|
n.addr := slv(unsigned(r.addr) + 1);
|
end if;
|
end if;
|
if r.waitstep = '1' then
|
if r.waitstep = '1' then
|
irb_busy := '1';
|
irb_busy := '1';
|
| Line 373... |
Line 381... |
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
icpaddr := cp_addr_init;
|
icpaddr := cp_addr_init;
|
|
icpaddr.be := r.membe;
|
|
|
|
if r.rbseli = '0' then -- access via cp
|
icpaddr.addr := r.addr;
|
icpaddr.addr := r.addr;
|
icpaddr.racc := '0';
|
icpaddr.racc := '0';
|
icpaddr.be := "11";
|
|
icpaddr.ena_22bit := r.ena_22bit;
|
icpaddr.ena_22bit := r.ena_22bit;
|
icpaddr.ena_ubmap := r.ena_ubmap;
|
icpaddr.ena_ubmap := r.ena_ubmap;
|
|
else -- access via ibus window
|
if r.rbseli = '1' and irbena = '1' then
|
|
icpaddr.addr(15 downto 13) := "111";
|
icpaddr.addr(15 downto 13) := "111";
|
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
|
icpaddr.addr(12 downto 1) := RB_MREQ.addr(11 downto 0);
|
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
|
|
icpaddr.racc := '1';
|
icpaddr.racc := '1';
|
icpaddr.be := r.ibrbe;
|
|
icpaddr.ena_22bit := '0';
|
icpaddr.ena_22bit := '0';
|
icpaddr.ena_ubmap := '0';
|
icpaddr.ena_ubmap := '0';
|
end if;
|
end if;
|
|
|
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
|
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
|
| Line 401... |
Line 408... |
RB_SRES.ack <= irb_ack;
|
RB_SRES.ack <= irb_ack;
|
RB_SRES.err <= irb_err;
|
RB_SRES.err <= irb_err;
|
RB_SRES.busy <= irb_busy;
|
RB_SRES.busy <= irb_busy;
|
RB_SRES.dout <= irb_dout;
|
RB_SRES.dout <= irb_dout;
|
|
|
RB_STAT(3) <= '0';
|
RB_STAT(3) <= CP_STAT.cmderr;
|
RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
|
RB_STAT(2) <= CP_STAT.cmdmerr;
|
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
|
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
|
RB_STAT(0) <= CP_STAT.cpugo;
|
RB_STAT(0) <= CP_STAT.cpugo;
|
|
|
RB_LAM <= irb_lam;
|
RB_LAM <= irb_lam;
|
|
|
