| Line 1... |
Line 1... |
-- $Id: pdp11_core_rbus.vhd 677 2015-05-09 21:52:32Z mueller $
|
-- $Id: pdp11_core_rbus.vhd 700 2015-07-12 19:28:31Z mueller $
|
--
|
--
|
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
--
|
--
|
-- This program is free software; you may redistribute and/or modify it under
|
-- This program is free software; you may redistribute and/or modify it under
|
-- the terms of the GNU General Public License as published by the Free
|
-- the terms of the GNU General Public License as published by the Free
|
| Line 25... |
Line 25... |
-- Date Rev ise Target flop lutl lutm slic t peri
|
-- Date Rev ise Target flop lutl lutm slic t peri
|
-- 2014-12-21 591 14.7 131013 xc6slx16-2 52 118 0 58 s 4.9
|
-- 2014-12-21 591 14.7 131013 xc6slx16-2 52 118 0 58 s 4.9
|
--
|
--
|
-- Revision History: -
|
-- Revision History: -
|
-- Date Rev Version Comment
|
-- Date Rev Version Comment
|
|
-- 2015-07-10 700 1.5.1 add cpuact logic, redefine lam as cpuact 1->0
|
-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul
|
-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul
|
-- 2014-12-26 621 1.4 use full size 4k word ibus window
|
-- 2014-12-26 621 1.4 use full size 4k word ibus window
|
-- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr
|
-- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr
|
-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT
|
-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT
|
-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
|
-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
|
| Line 125... |
Line 126... |
|
|
|
|
architecture syn of pdp11_core_rbus is
|
architecture syn of pdp11_core_rbus is
|
|
|
type state_type is (
|
type state_type is (
|
s_idle, -- s_idle: wait for rp access
|
s_idle, -- s_idle: wait for rbus access
|
s_cpwait, -- s_cpwait: wait for cp port ack
|
s_cpwait, -- s_cpwait: wait for cp port ack
|
s_cpstep -- s_cpstep: wait for cpustep done
|
s_cpstep -- s_cpstep: wait for cpustep done
|
);
|
);
|
|
|
type regs_type is record
|
type regs_type is record
|
| Line 137... |
Line 138... |
rbselc : slbit; -- rbus select for core
|
rbselc : slbit; -- rbus select for core
|
rbseli : slbit; -- rbus select for ibus
|
rbseli : slbit; -- rbus select for ibus
|
rbinit : slbit; -- rbus init seen (1 cycle pulse)
|
rbinit : slbit; -- rbus init seen (1 cycle pulse)
|
cpreq : slbit; -- cp request flag
|
cpreq : slbit; -- cp request flag
|
cpfunc : slv5; -- cp function
|
cpfunc : slv5; -- cp function
|
cpugo_1 : slbit; -- prev cycle cpugo
|
cpuact_1 : slbit; -- prev cycle cpuact
|
addr : slv22_1; -- address register
|
addr : slv22_1; -- address register
|
ena_22bit : slbit; -- 22bit enable
|
ena_22bit : slbit; -- 22bit enable
|
ena_ubmap : slbit; -- ubmap enable
|
ena_ubmap : slbit; -- ubmap enable
|
membe : slv2; -- memory write byte enables
|
membe : slv2; -- memory write byte enables
|
membestick : slbit; -- memory write byte enables sticky
|
membestick : slbit; -- memory write byte enables sticky
|
| Line 153... |
Line 154... |
s_idle, -- state
|
s_idle, -- state
|
'0','0', -- rbselc,rbseli
|
'0','0', -- rbselc,rbseli
|
'0', -- rbinit
|
'0', -- rbinit
|
'0', -- cpreq
|
'0', -- cpreq
|
(others=>'0'), -- cpfunc
|
(others=>'0'), -- cpfunc
|
'0', -- cpugo_1
|
'0', -- cpuact_1
|
(others=>'0'), -- addr
|
(others=>'0'), -- addr
|
'0','0', -- ena_22bit, ena_ubmap
|
'0','0', -- ena_22bit, ena_ubmap
|
"11",'0', -- membe,membestick
|
"11",'0', -- membe,membestick
|
'0','0' -- doinc, waitstep
|
'0','0' -- doinc, waitstep
|
);
|
);
|
| Line 190... |
Line 191... |
variable irb_err : slbit := '0';
|
variable irb_err : slbit := '0';
|
variable irb_dout : slv16 := (others=>'0');
|
variable irb_dout : slv16 := (others=>'0');
|
variable irb_lam : slbit := '0';
|
variable irb_lam : slbit := '0';
|
variable irbena : slbit := '0';
|
variable irbena : slbit := '0';
|
|
|
|
variable icpuact : slbit := '0';
|
variable icpreq : slbit := '0';
|
variable icpreq : slbit := '0';
|
variable icpaddr : cp_addr_type := cp_addr_init;
|
variable icpaddr : cp_addr_type := cp_addr_init;
|
|
|
begin
|
begin
|
|
|
| Line 405... |
Line 407... |
icpaddr.racc := '1';
|
icpaddr.racc := '1';
|
icpaddr.ena_22bit := '0';
|
icpaddr.ena_22bit := '0';
|
icpaddr.ena_ubmap := '0';
|
icpaddr.ena_ubmap := '0';
|
end if;
|
end if;
|
|
|
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
|
icpuact := CP_STAT.cpugo and not CP_STAT.suspint;
|
if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ?
|
n.cpuact_1 := icpuact; -- delay cpuact
|
|
if (r.cpuact_1='1' and icpuact='0') then -- cpuact 1 -> 0
|
irb_lam := '1';
|
irb_lam := '1';
|
end if;
|
end if;
|
|
|
N_REGS <= n;
|
N_REGS <= n;
|
|
|
