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Line 1... |
-- $Id: pdp11_tmu.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: pdp11_tmu.vhd 333 2010-10-17 21:18:33Z mueller $
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--
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- Dependencies: -
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-- Dependencies: -
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--
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--
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Target Devices: generic
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-- Tool versions: ghdl 0.18-0.25
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-- Tool versions: ghdl 0.18-0.25
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2010-10-17 333 1.0.6 use ibus V2 interface
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
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-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
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-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
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Line 95... |
write(oline, string'(" dp.gpr_adst:o"));
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write(oline, string'(" dp.gpr_adst:o"));
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write(oline, string'(" dp.gpr_mode:o"));
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write(oline, string'(" dp.gpr_mode:o"));
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write(oline, string'(" dp.gpr_bytop:b"));
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write(oline, string'(" dp.gpr_bytop:b"));
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write(oline, string'(" dp.gpr_we:b"));
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write(oline, string'(" dp.gpr_we:b"));
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write(oline, string'(" vm.ibmreq.req:b"));
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write(oline, string'(" vm.ibmreq.aval:b"));
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write(oline, string'(" vm.ibmreq.re:b"));
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write(oline, string'(" vm.ibmreq.we:b"));
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write(oline, string'(" vm.ibmreq.we:b"));
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write(oline, string'(" vm.ibmreq.rmw:b"));
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write(oline, string'(" vm.ibmreq.be0:b"));
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write(oline, string'(" vm.ibmreq.be0:b"));
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write(oline, string'(" vm.ibmreq.be1:b"));
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write(oline, string'(" vm.ibmreq.be1:b"));
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write(oline, string'(" vm.ibmreq.dip:b"));
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write(oline, string'(" vm.ibmreq.cacc:b"));
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write(oline, string'(" vm.ibmreq.cacc:b"));
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write(oline, string'(" vm.ibmreq.racc:b"));
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write(oline, string'(" vm.ibmreq.racc:b"));
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write(oline, string'(" vm.ibmreq.addr:o"));
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write(oline, string'(" vm.ibmreq.addr:o"));
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write(oline, string'(" vm.ibmreq.din:o"));
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write(oline, string'(" vm.ibmreq.din:o"));
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write(oline, string'(" vm.ibsres.ack:b"));
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write(oline, string'(" vm.ibsres.ack:b"));
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| Line 144... |
Line 147... |
DM_STAT_DP.gpr_we='1' or
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DM_STAT_DP.gpr_we='1' or
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DM_STAT_SY.emmreq.req='1' or
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DM_STAT_SY.emmreq.req='1' or
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DM_STAT_SY.emsres.ack_r='1' or
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DM_STAT_SY.emsres.ack_r='1' or
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DM_STAT_SY.emsres.ack_w='1' or
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DM_STAT_SY.emsres.ack_w='1' or
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DM_STAT_SY.emmreq.cancel='1' or
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DM_STAT_SY.emmreq.cancel='1' or
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DM_STAT_VM.ibmreq.req='1' or
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DM_STAT_VM.ibmreq.re='1' or
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DM_STAT_VM.ibmreq.we='1' or
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DM_STAT_VM.ibsres.ack='1'
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DM_STAT_VM.ibsres.ack='1'
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then
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then
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wcycle := true;
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wcycle := true;
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end if;
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end if;
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| Line 177... |
Line 181... |
writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
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writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
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write(oline, DM_STAT_DP.gpr_bytop, right, 2);
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write(oline, DM_STAT_DP.gpr_bytop, right, 2);
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write(oline, DM_STAT_DP.gpr_we, right, 2);
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write(oline, DM_STAT_DP.gpr_we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.req, right, 2);
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write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
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write(oline, DM_STAT_VM.ibmreq.re, right, 2);
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write(oline, DM_STAT_VM.ibmreq.we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.we, right, 2);
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write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
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write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
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write(oline, DM_STAT_VM.ibmreq.dip, right, 2);
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write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
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write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
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writeoct(oline, ibaddr, right, 7);
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writeoct(oline, ibaddr, right, 7);
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writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
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writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
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write(oline, DM_STAT_VM.ibsres.ack, right, 2);
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write(oline, DM_STAT_VM.ibsres.ack, right, 2);
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