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-- $Id: tb_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $
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-- $Id: tb_pdp11core.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- the terms of the GNU General Public License as published by the Free
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
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-- 2007-10-07 88 - 0.26 - - c:ok
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-- 2007-10-07 88 - 0.26 - - c:ok
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--
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--
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-- Revision History:
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-- Revision History:
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-- Date Rev Version Comment
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-- Date Rev Version Comment
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-- 2011-12-23 444 1.4 use new simclk/simclkcnt
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-- 2011-11-18 427 1.3.2 now numeric_std clean
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-- 2011-11-18 427 1.3.2 now numeric_std clean
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
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signal CP_STAT_cpuhalt : slbit := '0';
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signal CP_STAT_cpuhalt : slbit := '0';
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signal CP_STAT_cpurust : slv4 := (others=>'0');
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signal CP_STAT_cpurust : slv4 := (others=>'0');
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signal CP_DOUT : slv16 := (others=>'0');
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signal CP_DOUT : slv16 := (others=>'0');
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signal CLK_STOP : slbit := '0';
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signal CLK_STOP : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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signal R_CHKDAT : slv16 := (others=>'0');
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signal R_CHKDAT : slv16 := (others=>'0');
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signal R_CHKMSK : slv16 := (others=>'0');
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signal R_CHKMSK : slv16 := (others=>'0');
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signal R_CHKREQ : slbit := '0';
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signal R_CHKREQ : slbit := '0';
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signal R_CP_STAT : cp_stat_type := cp_stat_init;
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signal R_CP_STAT : cp_stat_type := cp_stat_init;
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signal R_CP_DOUT : slv16 := (others=>'0');
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signal R_CP_DOUT : slv16 := (others=>'0');
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begin
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begin
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SYSCLK : simclk
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CLKGEN : simclk
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generic map (
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generic map (
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PERIOD => clock_period,
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PERIOD => clock_period,
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OFFSET => clock_offset)
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OFFSET => clock_offset)
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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CLK_CYCLE => SB_CLKCYCLE,
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CLK_STOP => CLK_STOP
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CLK_STOP => CLK_STOP
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);
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);
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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UUT: entity work.tbd_pdp11core
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UUT: entity work.tbd_pdp11core
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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RESET => RESET,
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RESET => RESET,
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CP_CNTL_req => CP_CNTL_req,
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CP_CNTL_req => CP_CNTL_req,
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end loop;
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end loop;
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wait for 4*clock_period;
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wait for 4*clock_period;
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CLK_STOP <= '1';
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CLK_STOP <= '1';
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writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
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writetimestamp(oline, CLK_CYCLE, ": DONE ");
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writeline(output, oline);
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writeline(output, oline);
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wait; -- suspend proc_stim forever
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wait; -- suspend proc_stim forever
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-- clock is stopped, sim will end
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-- clock is stopped, sim will end
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