| Line 1... |
Line 1... |
#!/usr/bin/perl -w
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#!/usr/bin/perl -w
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# $Id: vbomconv 575 2014-07-27 20:55:41Z mueller $
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# $Id: vbomconv 646 2015-02-15 12:04:55Z mueller $
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#
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#
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# Copyright 2007-2014 by Walter F.J. Mueller
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# Copyright 2007-2015 by Walter F.J. Mueller
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#
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#
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# This program is free software; you may redistribute and/or modify it under
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation, either version 2, or at your option any later version.
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# Software Foundation, either version 2, or at your option any later version.
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#
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#
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| Line 12... |
Line 12... |
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for complete details.
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# for complete details.
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#
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#
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# Revision History:
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# Revision History:
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# Date Rev Version Comment
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# Date Rev Version Comment
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# 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead
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# of XTWI_PATH; drop --ise_path; add @lib:unimacro;
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# drop --viv_vhdl; add --vsyn_prj, --dep_vsyn;
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# drop cygwin support;
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# 2014-07-26 575 1.10.1 use XTWI_PATH now (ise/vivado switch done later)
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# 2014-07-26 575 1.10.1 use XTWI_PATH now (ise/vivado switch done later)
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# 2013-10-20 543 1.10 add --viv_vhdl
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# 2013-10-20 543 1.10 add --viv_vhdl
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# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
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# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
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# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
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# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
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# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
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# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
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| Line 38... |
Line 42... |
# 2007-12-17 102 1.7.1 fix @ucf_cpp logic.
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# 2007-12-17 102 1.7.1 fix @ucf_cpp logic.
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# 2007-12-16 101 1.7 add @ucf_cpp pseudo tag (handle cpp'ed ucf files)
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# 2007-12-16 101 1.7 add @ucf_cpp pseudo tag (handle cpp'ed ucf files)
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# 2007-11-25 98 1.6.1 drop trailing blanks on input lines
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# 2007-11-25 98 1.6.1 drop trailing blanks on input lines
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# 2007-11-02 94 1.6 added (xst|ghdl)_export
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# 2007-11-02 94 1.6 added (xst|ghdl)_export
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# 2007-10-26 92 1.5.1 emit '--no-vital-checks' for --ghdl_m for _[sft]sim
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# 2007-10-26 92 1.5.1 emit '--no-vital-checks' for --ghdl_m for _[sft]sim
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# 2007-10-14 98 1.5 handle .exe files under cycwin properly
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# 2007-10-14 98 1.5 handle .exe files under cygwin properly
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# 2007-09-15 82 1.4 handle C source objects properly
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# 2007-09-15 82 1.4 handle C source objects properly
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# 2007-08-10 72 1.3 add [xst], [ghdl] prefix support
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# 2007-08-10 72 1.3 add [xst], [ghdl] prefix support
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# 2007-07-22 68 1.2 add "tag = val"; list files in 'ready to analyse'
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# 2007-07-22 68 1.2 add "tag = val"; list files in 'ready to analyse'
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# order; add --ghdl_a option
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# order; add --ghdl_a option
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# 2007-07-08 65 1.1 add "tag : names"; inferral of _[ft]sim vboms
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# 2007-07-08 65 1.1 add "tag : names"; inferral of _[ft]sim vboms
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| Line 54... |
Line 58... |
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use Getopt::Long;
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use Getopt::Long;
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|
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my %opts = ();
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my %opts = ();
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|
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GetOptions(\%opts, "help", "trace", "ise_path=s",
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GetOptions(\%opts, "help", "trace", "xlpath=s",
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"dep_xst", "dep_ghdl", "dep_isim",
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"dep_ghdl", "dep_xst", "dep_isim", "dep_vsyn",
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"xst_prj", "isim_prj",
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"xst_prj", "isim_prj",
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"viv_vhdl",
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"vsyn_prj",
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"ghdl_a", "ghdl_a_cmd",
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"ghdl_a", "ghdl_a_cmd",
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"ghdl_i", "ghdl_i_cmd",
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"ghdl_i", "ghdl_i_cmd",
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"ghdl_m", "ghdl_m_cmd",
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"ghdl_m", "ghdl_m_cmd",
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"xst_export=s",
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"ghdl_export=s",
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"ghdl_export=s",
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"xst_export=s",
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"isim_export=s",
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"isim_export=s",
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"get_top",
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"get_top",
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"flist") || exit 1;
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"flist") || exit 1;
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sub print_help;
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sub print_help;
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| Line 74... |
Line 78... |
sub scan_vbom;
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sub scan_vbom;
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sub copy_edir;
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sub copy_edir;
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sub write_vbomdep;
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sub write_vbomdep;
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sub canon_fname;
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sub canon_fname;
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|
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my @vbom_list;
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my @vbom_queue; # list of pending vbom's
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my @file_list;
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my @srcfile_list; # list of sources in compile order
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my %vbom_tbl;
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my @xdcfile_list; # list of xdc files
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my %file_tbl;
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my %vbom_files; # key=vbom; val=full file list
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my %read_tbl;
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my %vbom_xdc; # key=vbom; val=xdc spec list
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my %para_tbl;
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my %vbom_done; # key=vbom; val=done flags
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my %vbom_rank; # key=vbom; val=vbom ranks
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my %srcfile_rank; # key=source file; val=file rank
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my %para_tbl; # substitution table
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my @ucf_cpp_list;
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my @ucf_cpp_list;
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my $is_xst = 0; # XST synthesis target
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my $is_ghdl = 0; # ghdl simulation target
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my $is_ghdl = 0; # ghdl simulation target
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my $is_xst = 0; # XST synthesis target
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my $is_isim = 0; # ISim simulation target
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my $is_isim = 0; # ISim simulation target
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my $is_vsyn = 0; # vivado synthesis target
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my $is_vsim = 0; # vivado simulation target
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my $is_sim = 0; # simulation target (generic)
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my $is_sim = 0; # simulation target (generic)
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my $is_any = 0;
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my $is_any = 0; # ignore tags (for --flist)
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my $nactions = 0;
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my $nactions = 0; # number of action commands
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my $top_vbom;
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my $top_vbom; # top level vbom (from argv)
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my $stem;
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my $stem; # stem of $top_vbom
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my $top;
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my $top; # top level entity name
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my $top_done = 0;
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my $top_done = 0; # @top seen
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my $has_unisim;
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my $has_unisim; # @lib:unisim seen or implied
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my $has_simprim;
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my $has_unimacro; # @lib:unimacro seen
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my $has_simprim; # @lib:simprim seen or implied
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my $is_ssim;
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my $is_ssim;
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my $is_fsim;
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my $is_fsim;
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my $is_tsim;
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my $is_tsim;
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my $do_trace = exists $opts{trace};
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my $do_trace = exists $opts{trace};
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my $level;
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my $level = 0; # vbom nesting level
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my $xst_writevhdl = 1;
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my $xst_writevhdl = 1;
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my $xlpath=$opts{xlpath};
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my $no_xlpath = ! defined $xlpath || $xlpath eq "";
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# now using '-ifmt mixed', so language always needed (2011-08-13)
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autoflush STDOUT 1; # autoflush, so nothing lost on exec later
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#if (defined $opts{ise_path}) {
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# if ($opts{ise_path} =~ /^xc6s/) {
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# $xst_writevhdl = 0;
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# }
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#}
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|
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autoflush STDOUT 1; # autoflush, so noting lost on exec later
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|
|
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if (exists $opts{help}) {
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if (exists $opts{help}) {
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print_help;
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print_help;
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exit 0;
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exit 0;
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}
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}
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# ensure that one and only one vbom is specified
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# ensure that one and only one vbom is specified
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|
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if (scalar(@ARGV) != 1) {
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if (scalar(@ARGV) != 1) {
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print STDERR "%vbomconv-E: only one vbom file name allowed\n\n";
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print STDERR "vbomconv-E: only one vbom file name allowed\n\n";
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print_help;
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print_help;
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exit 1;
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exit 1;
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}
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}
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|
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# check that only one action is defined, mark xst, gdhl, or isim class
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# check that only one action is defined, mark xst, gdhl, or isim class
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|
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foreach (keys %opts) {
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foreach (keys %opts) {
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$nactions += 1 unless ($_ eq "trace" || $_ eq "ise_path");
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$nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath");
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$is_xst = 1 if ($_ eq "dep_xst");
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$is_ghdl = 1 if ($_ eq "dep_ghdl");
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$is_ghdl = 1 if ($_ eq "dep_ghdl");
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$is_isim = 1 if ($_ eq "dep_isim");
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$is_xst = 1 if ($_ =~ /^xst_/);
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$is_ghdl = 1 if ($_ =~ /^ghdl_/);
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$is_ghdl = 1 if ($_ =~ /^ghdl_/);
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$is_xst = 1 if ($_ eq "dep_xst");
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$is_xst = 1 if ($_ =~ /^xst_/);
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$is_isim = 1 if ($_ eq "dep_isim");
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$is_isim = 1 if ($_ =~ /^isim_/);
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$is_isim = 1 if ($_ =~ /^isim_/);
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$is_vsyn = 1 if ($_ eq "dep_vsyn");
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$is_vsyn = 1 if ($_ =~ /^vsyn_/);
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$is_any = 1 if ($_ eq "flist");
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$is_any = 1 if ($_ eq "flist");
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}
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}
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$is_sim = $is_ghdl | $is_isim;
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$is_sim = $is_ghdl | $is_isim | $is_vsim;
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print STDERR "-- [xst] active\n" if $do_trace && $is_xst;
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print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl;
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print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl;
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print STDERR "-- [xst] active\n" if $do_trace && $is_xst;
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print STDERR "-- [isim] active\n" if $do_trace && $is_isim;
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print STDERR "-- [isim] active\n" if $do_trace && $is_isim;
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print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn;
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print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim;
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print STDERR "-- [sim] active\n" if $do_trace && $is_sim;
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print STDERR "-- [sim] active\n" if $do_trace && $is_sim;
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|
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if ($nactions > 1) {
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if ($nactions > 1) {
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print STDERR "%vbomconv-E: only one action qualifier allowed\n\n";
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print STDERR "vbomconv-E: only one action qualifier allowed\n\n";
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print_help;
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print_help;
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exit 1;
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exit 1;
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}
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}
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|
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$top_vbom = $ARGV[0];
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$top_vbom = $ARGV[0];
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| Line 175... |
Line 188... |
$top_vbom =~ s{_tsim\.vbom$}{_ssim.vbom};
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$top_vbom =~ s{_tsim\.vbom$}{_ssim.vbom};
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}
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}
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# traverse all vbom's start with command line argument
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# traverse all vbom's start with command line argument
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push @vbom_list, $top_vbom;
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push @vbom_queue, $top_vbom;
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|
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while (@vbom_list) {
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while (@vbom_queue) {
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my $cur_vbom = shift @vbom_list;
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my $cur_vbom = shift @vbom_queue;
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read_vbom($cur_vbom);
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read_vbom($cur_vbom);
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}
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}
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|
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# traverse internal vbom representation to build file table
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# traverse internal vbom representation to build file table
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|
|
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$vbom_rank{$top_vbom} = {min=>1, max=>1};
|
scan_vbom($top_vbom);
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scan_vbom($top_vbom);
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|
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# sort file table, build file list (decreasing rank)
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# sort file table, build file list (decreasing rank)
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# sort first by decreasing rank and second by filename
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# second sort only to get stable sequence, independent of hash keys
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|
|
my @pair_list;
|
my @srcpair_list;
|
foreach (keys %file_tbl) {
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foreach (keys %srcfile_rank) {
|
push @pair_list, [$file_tbl{$_}, $_];
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push @srcpair_list, [$srcfile_rank{$_}, $_];
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|
}
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|
|
|
@srcfile_list = map {$_->[1]}
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sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]}
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@srcpair_list;
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|
|
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# setup vbom list by rank
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my @vbom_rank_list;
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foreach (sort keys %vbom_rank) {
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push @vbom_rank_list, [$vbom_rank{$_}{min}, $vbom_rank{$_}{max}, $_];
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|
}
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my @vbomfile_list_min = map {$_->[2]}
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sort {$a->[0] <=> $b->[0] || $a->[1] cmp $b->[1]}
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@vbom_rank_list;
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|
|
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# setup xdc files list (if one @xdc: seen)
|
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foreach (@vbomfile_list_min) {
|
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push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_};
|
}
|
}
|
|
|
@file_list = map {$_->[1]} sort {$b->[0] <=> $a->[0]} @pair_list;
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|
|
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# now generate output and actions, depending on options given
|
# now generate output and actions, depending on options given
|
|
|
# --trace ------------------------------------------------------------
|
# --trace ------------------------------------------------------------
|
|
|
if ($do_trace) {
|
if ($do_trace) {
|
print STDERR "\n";
|
print STDERR "\n";
|
print STDERR "filename substitution table:\n";
|
print STDERR "filename substitution table:\n";
|
foreach (sort keys %para_tbl) {
|
foreach (sort keys %para_tbl) {
|
print STDERR " $_ = $para_tbl{$_}\n";
|
print STDERR " $_ = $para_tbl{$_}\n";
|
}
|
}
|
print STDERR "final file_list:\n";
|
|
foreach (@file_list) {
|
print STDERR "\n";
|
print STDERR " $_\n";
|
print STDERR "final vbom_rank table (sort by min rank):\n";
|
|
print STDERR " min max var vbom-name:\n";
|
|
foreach (sort {$a->[0] <=> $b->[0] || $a->[2] cmp $b->[2]} @vbom_rank_list) {
|
|
printf STDERR " %3d %3d %3d %s\n",
|
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$_->[0], $_->[1], $_->[1]-$_->[0], $_->[2];
|
}
|
}
|
|
|
|
print STDERR "\n";
|
|
print STDERR "final srcfile_rank table (sort by rank):\n";
|
|
foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) {
|
|
printf STDERR " %5d %s\n", $_->[0], $_->[1];
|
|
}
|
|
|
|
print STDERR "\n";
|
print STDERR "properties:\n";
|
print STDERR "properties:\n";
|
print STDERR " \@top: $top\n";
|
print STDERR " \@top: $top\n";
|
}
|
}
|
|
|
# --ghdh_a -- ghdl analysis command ----------------------------------
|
# --ghdh_a -- ghdl analysis command ----------------------------------
|
|
|
if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) {
|
if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) {
|
foreach (@file_list) {
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
|
print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd";
|
|
exit 1;
|
|
}
|
|
|
|
foreach (@srcfile_list) {
|
my $file = $_;
|
my $file = $_;
|
my $cmd = "ghdl -a";
|
my $cmd = "ghdl -a";
|
$cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/unisim' if $has_unisim;
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/simprim' if $has_simprim;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " $file";
|
$cmd .= " $file";
|
print "$cmd\n";
|
print "$cmd\n";
|
if (exists $opts{ghdl_a}) {
|
if (exists $opts{ghdl_a}) {
|
my $wrc = system "/bin/sh", "-c", $cmd;
|
my $wrc = system "/bin/sh", "-c", $cmd;
|
if ($wrc != 0) {
|
if ($wrc != 0) {
|
my $rc = int($wrc/256);
|
my $rc = int($wrc/256);
|
if ($rc == 0) {
|
if ($rc == 0) {
|
my $sig = $wrc % 256;
|
my $sig = $wrc % 256;
|
print STDERR "%vbomconv-I: compilation aborted by signal $sig\n";
|
print STDERR "vbomconv-I: compilation aborted by signal $sig\n";
|
exit(1);
|
exit(1);
|
} else {
|
} else {
|
print STDERR "%vbomconv-I: compilation failed (rc=$rc) $?\n";
|
print STDERR "vbomconv-I: compilation failed (rc=$rc) $?\n";
|
exit($rc);
|
exit($rc);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
| Line 265... |
Line 315... |
}
|
}
|
|
|
my $cmd = "ghdl -i";
|
my $cmd = "ghdl -i";
|
my $nfile = 0;
|
my $nfile = 0;
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
next if /\.c$/; # skip C sources, only vhd handled
|
next if /\.c$/; # skip C sources, only vhd handled
|
if (not exists $ghdl_work{$_}) {
|
if (not exists $ghdl_work{$_}) {
|
$cmd .= " \\\n $_";
|
$cmd .= " \\\n $_";
|
$nfile += 1;
|
$nfile += 1;
|
}
|
}
|
| Line 294... |
Line 344... |
# the right thing.
|
# the right thing.
|
|
|
if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) {
|
if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) {
|
my $cmd = "";
|
my $cmd = "";
|
|
|
if (-r "$stem.exe") { # check for .exe, in case we are in cygwin
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) {
|
$cmd .= "rm $stem.exe\n"; # rm old executable to force elaboration
|
print STDERR "vbomconv-E: --xlpath required with ghdl_m or ghdl_m_cmd";
|
} elsif (-r $stem) { # otherwise
|
exit 1;
|
$cmd .= "rm $stem\n" ; # rm old executable to force elaboration
|
}
|
|
|
|
if (-r $stem) { # check for old executable
|
|
$cmd .= "rm $stem\n" ; # rm to force elaboration
|
}
|
}
|
|
|
$cmd .= "ghdl -m";
|
$cmd .= "ghdl -m";
|
$cmd .= " -o $stem";
|
$cmd .= " -o $stem";
|
# -fexplicit needed for ISE 13.1,13.3
|
# -fexplicit needed for ISE 13.1,13.3
|
$cmd .= ' -fexplicit' if $has_unisim or $has_simprim;
|
$cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim;
|
$cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/unisim' if $has_unisim;
|
$cmd .= " -P$xlpath/unisim" if $has_unisim;
|
$cmd .= ' -P$XTWI_PATH/ISE_DS/ISE/ghdl/simprim' if $has_simprim;
|
$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
|
|
$cmd .= " -P$xlpath/simprim" if $has_simprim;
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " --ieee=synopsys";
|
$cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_tsim;
|
$cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_tsim;
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
next unless /\.c$/; # C source ?
|
next unless /\.c$/; # C source ?
|
my $ofile = $_; # copy to break alias for following s///
|
my $ofile = $_; # copy to break alias for following s///
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s/\.c$/.o/; # add clause to link C source object file
|
$ofile =~ s/\.c$/.o/; # add clause to link C source object file
|
$cmd .= " -Wl,$ofile";
|
$cmd .= " -Wl,$ofile";
|
| Line 327... |
Line 381... |
}
|
}
|
|
|
# --xst_prj ----------------------------------------------------------
|
# --xst_prj ----------------------------------------------------------
|
|
|
if (exists $opts{xst_prj}) {
|
if (exists $opts{xst_prj}) {
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
if ($xst_writevhdl) {
|
if ($xst_writevhdl) {
|
print "vhdl work $_\n";
|
print "vhdl work $_\n";
|
} else {
|
} else {
|
print "work $_\n"; # for ISE S-6/V-6 compilations with '-ifmt VHDL'
|
print "work $_\n"; # for ISE S-6/V-6 compilations with '-ifmt VHDL'
|
}
|
}
|
| Line 339... |
Line 393... |
}
|
}
|
|
|
# --isim_prj ---------------------------------------------------------
|
# --isim_prj ---------------------------------------------------------
|
|
|
if (exists $opts{isim_prj}) {
|
if (exists $opts{isim_prj}) {
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
print "vhdl work $_\n";
|
print "vhdl work $_\n";
|
}
|
}
|
}
|
}
|
|
|
# --viv_vhdl ---------------------------------------------------------
|
# --vsyn_prj ---------------------------------------------------------
|
|
|
if (exists $opts{viv_vhdl}) {
|
if (exists $opts{vsyn_prj}) {
|
print "read_vhdl {\n";
|
# setup sources
|
foreach (@file_list) {
|
print "#\n";
|
|
print "# setup sources\n";
|
|
print "#\n";
|
|
print "set src_files {\n";
|
|
foreach (@srcfile_list) {
|
print " $_\n";
|
print " $_\n";
|
}
|
}
|
print "}\n";
|
print "}\n";
|
}
|
print "\n";
|
|
|
# --dep_xst ----------------------------------------------------------
|
print "set obj [get_filesets sources_1]\n";
|
|
print "add_files -norecurse -fileset \$obj \$src_files\n";
|
|
print "set_property \"top\" \"$top\" \$obj\n";
|
|
|
if (exists $opts{dep_xst}) {
|
# setup constraints
|
print "#\n";
|
|
print "$stem.ngc : $stem.dep_xst\n";
|
|
print "#\n";
|
|
foreach (@file_list) {
|
|
print "$stem.ngc : $_\n";
|
|
}
|
|
# handle cpp preprocessed ucf's
|
|
foreach (@ucf_cpp_list) {
|
|
my $file = $_;
|
|
$file =~ s/\.ucf$//;
|
|
print "#\n";
|
print "#\n";
|
print "$file.ncd : $file.ucf\n";
|
print "# setup constraints\n";
|
print "include $file.dep_ucf_cpp\n";
|
|
}
|
|
# handle plain ucf's
|
|
if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") {
|
|
print "#\n";
|
print "#\n";
|
print "$stem.ncd : $stem.ucf\n";
|
|
|
print "set xdc_files {\n";
|
|
foreach (@xdcfile_list) {
|
|
print " $_\n";
|
}
|
}
|
write_vbomdep("$stem.dep_xst");
|
print "}\n";
|
|
print "\n";
|
|
|
|
print "set obj [get_filesets constrs_1]\n";
|
|
print "add_files -norecurse -fileset \$obj \$xdc_files\n";
|
|
|
|
print "\n";
|
}
|
}
|
|
|
# --dep_ghdl ---------------------------------------------------------
|
# --dep_ghdl ---------------------------------------------------------
|
|
|
if (exists $opts{dep_ghdl}) {
|
if (exists $opts{dep_ghdl}) {
|
| Line 396... |
Line 451... |
print "$stem_fsim : $stem.dep_ghdl\n";
|
print "$stem_fsim : $stem.dep_ghdl\n";
|
print "$stem_tsim : $stem.dep_ghdl\n";
|
print "$stem_tsim : $stem.dep_ghdl\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
if (/\.c$/) {
|
if (/\.c$/) {
|
my $ofile = $_; # copy to break alias for following s///
|
my $ofile = $_; # copy to break alias for following s///
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s{^.*/}{}; # remove directory path
|
$ofile =~ s/\.c$/.o/; # object file name
|
$ofile =~ s/\.c$/.o/; # object file name
|
print "$stem : $ofile\n"; # depend on C source object file
|
print "$stem : $ofile\n"; # depend on C source object file
|
| Line 415... |
Line 470... |
}
|
}
|
}
|
}
|
|
|
if ($is_ssim) {
|
if ($is_ssim) {
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
if (/\.c$/) {
|
if (/\.c$/) {
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
} else {
|
} else {
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
}
|
}
|
print "$stem_fsim : $file\n";
|
print "$stem_fsim : $file\n";
|
}
|
}
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
if (/\.c$/) {
|
if (/\.c$/) {
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s{^.*/}{}; # remove directory path
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
} else {
|
} else {
|
| Line 443... |
Line 498... |
|
|
write_vbomdep("$stem.dep_ghdl");
|
write_vbomdep("$stem.dep_ghdl");
|
|
|
}
|
}
|
|
|
|
# --dep_xst ----------------------------------------------------------
|
|
|
|
if (exists $opts{dep_xst}) {
|
|
print "#\n";
|
|
print "$stem.ngc : $stem.dep_xst\n";
|
|
print "#\n";
|
|
foreach (@srcfile_list) {
|
|
print "$stem.ngc : $_\n";
|
|
}
|
|
# handle cpp preprocessed ucf's
|
|
foreach (@ucf_cpp_list) {
|
|
my $file = $_;
|
|
$file =~ s/\.ucf$//;
|
|
print "#\n";
|
|
print "$file.ncd : $file.ucf\n";
|
|
print "include $file.dep_ucf_cpp\n";
|
|
}
|
|
# handle plain ucf's
|
|
if (scalar(@ucf_cpp_list)==0 && -r "$stem.ucf") {
|
|
print "#\n";
|
|
print "$stem.ncd : $stem.ucf\n";
|
|
}
|
|
write_vbomdep("$stem.dep_xst");
|
|
}
|
|
|
# --dep_isim ---------------------------------------------------------
|
# --dep_isim ---------------------------------------------------------
|
|
|
if (exists $opts{dep_isim}) {
|
if (exists $opts{dep_isim}) {
|
my $stem_isim = $stem . "_ISim";
|
my $stem_isim = $stem . "_ISim";
|
|
|
| Line 463... |
Line 543... |
print "$stem_fsim_isim : $stem.dep_isim\n";
|
print "$stem_fsim_isim : $stem.dep_isim\n";
|
print "$stem_tsim_isim : $stem.dep_isim\n";
|
print "$stem_tsim_isim : $stem.dep_isim\n";
|
}
|
}
|
print "#\n";
|
print "#\n";
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
print "$stem_isim : $_\n";
|
print "$stem_isim : $_\n";
|
}
|
}
|
|
|
if ($is_ssim) {
|
if ($is_ssim) {
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
print "$stem_fsim_isim : $file\n";
|
print "$stem_fsim_isim : $file\n";
|
}
|
}
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
my $file = $_; # copy to break alias for following s///
|
my $file = $_; # copy to break alias for following s///
|
$file =~ s/_ssim\.vhd$/_tsim.vhd/;
|
$file =~ s/_ssim\.vhd$/_tsim.vhd/;
|
print "$stem_tsim_isim : $file\n";
|
print "$stem_tsim_isim : $file\n";
|
}
|
}
|
|
|
}
|
}
|
|
|
write_vbomdep("$stem.dep_isim");
|
write_vbomdep("$stem.dep_isim");
|
}
|
}
|
|
|
# --xst_export or ghdl_export or isim_export -------------------------
|
# --dep_vsyn ---------------------------------------------------------
|
|
|
|
if (exists $opts{dep_vsyn}) {
|
|
print "#\n";
|
|
print "$stem.bit : $stem.dep_vsyn\n";
|
|
print "#\n";
|
|
my @files;
|
|
push @files, @srcfile_list;
|
|
push @files, @xdcfile_list;
|
|
foreach (@files) {
|
|
print "$stem.bit : $_\n";
|
|
}
|
|
print "#\n";
|
|
foreach (@files) {
|
|
print "${stem}_syn.dcp : $_\n";
|
|
}
|
|
print "#\n";
|
|
foreach (@files) {
|
|
print "${stem}_rou.dcp : $_\n";
|
|
}
|
|
write_vbomdep("$stem.dep_vsyn");
|
|
}
|
|
|
|
# --ghdl_export or xst_export or isim_export -------------------------
|
|
|
if (exists $opts{xst_export} or
|
if (exists $opts{ghdl_export} or
|
exists $opts{ghdl_export} or
|
exists $opts{xst_export} or
|
exists $opts{isim_export}) {
|
exists $opts{isim_export}) {
|
my $edir;
|
my $edir;
|
$edir = $opts{xst_export} if exists $opts{xst_export};
|
|
$edir = $opts{ghdl_export} if exists $opts{ghdl_export};
|
$edir = $opts{ghdl_export} if exists $opts{ghdl_export};
|
|
$edir = $opts{xst_export} if exists $opts{xst_export};
|
$edir = $opts{isim_export} if exists $opts{isim_export};
|
$edir = $opts{isim_export} if exists $opts{isim_export};
|
|
|
if (not -d $edir) {
|
if (not -d $edir) {
|
print STDERR "%vbomconv-I: create target directory $edir\n";
|
print STDERR "vbomconv-I: create target directory $edir\n";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
} else {
|
} else {
|
print STDERR "%vbomconv-I: target directory $edir already exists\n";
|
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
}
|
}
|
|
|
open(PFILE, ">$edir/$stem.prj") or die "can't write open $edir/$stem.prj: $!";
|
open(PFILE, ">$edir/$stem.prj") or die "can't write open $edir/$stem.prj: $!";
|
|
|
foreach (@file_list) {
|
foreach (@srcfile_list) {
|
my $fname = $_;
|
my $fname = $_;
|
my $fdpath = ".";
|
my $fdpath = ".";
|
if (m{(.*)/(.*)}) {
|
if (m{(.*)/(.*)}) {
|
$fname = $2;
|
$fname = $2;
|
$fdpath = $1;
|
$fdpath = $1;
|
| Line 547... |
Line 650... |
|
|
if (exists $opts{flist}) {
|
if (exists $opts{flist}) {
|
|
|
my @flist;
|
my @flist;
|
|
|
push @flist, @file_list;
|
push @flist, @srcfile_list;
|
push @flist, sort keys %read_tbl;
|
push @flist, sort keys %vbom_done;
|
|
|
if (scalar(@ucf_cpp_list)) {
|
if (scalar(@ucf_cpp_list)) {
|
foreach (@ucf_cpp_list) {
|
foreach (@ucf_cpp_list) {
|
push @flist, $_."_cpp";
|
push @flist, $_."_cpp";
|
}
|
}
|
| Line 560... |
Line 663... |
if (-r "$stem.ucf") {
|
if (-r "$stem.ucf") {
|
push @flist, "$stem.ucf";
|
push @flist, "$stem.ucf";
|
}
|
}
|
}
|
}
|
|
|
|
push @flist, @xdcfile_list;
|
|
|
foreach (sort @flist) {
|
foreach (sort @flist) {
|
my $fname = $_;
|
my $fname = $_;
|
my $fdpath = ".";
|
my $fdpath = ".";
|
if (m{(.*)/(.*)}) {
|
if (m{(.*)/(.*)}) {
|
$fname = $2;
|
$fname = $2;
|
| Line 588... |
Line 693... |
if ($vbom =~ m{^(.*)/([a-zA-Z0-9_.]*)$}) {
|
if ($vbom =~ m{^(.*)/([a-zA-Z0-9_.]*)$}) {
|
$vbom_path = $1;
|
$vbom_path = $1;
|
$vbom_file = $2;
|
$vbom_file = $2;
|
}
|
}
|
|
|
$read_tbl{$vbom} += 1; # mark this vbom already read
|
$vbom_done{$vbom} += 1; # mark this vbom already read
|
|
|
while () {
|
while () {
|
chomp;
|
chomp;
|
next if /^\s*#/; # drop comments
|
next if /^\s*#/; # drop comments
|
next if /^\s*$/; # drop empty lines
|
next if /^\s*$/; # drop empty lines
|
| Line 602... |
Line 707... |
# process parameter definitions
|
# process parameter definitions
|
if (m{([\w]+)\s*=\s*(.*)}) {
|
if (m{([\w]+)\s*=\s*(.*)}) {
|
my $para = $1;
|
my $para = $1;
|
my $val = $2;
|
my $val = $2;
|
if ($val eq "") {
|
if ($val eq "") {
|
print STDERR "%vbomconv-E: invalid \'$_\' in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid \'$_\' in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
if (not exists $para_tbl{$para}) {
|
if (not exists $para_tbl{$para}) {
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
$para_tbl{$para} = canon_fname($vbom_path, $val);
|
print STDERR "--- define \${$para} = $val\n" if $do_trace;
|
print STDERR "--- define \${$para} = $val\n" if $do_trace;
|
| Line 633... |
Line 738... |
}
|
}
|
if (defined $para_tbl{$para}) {
|
if (defined $para_tbl{$para}) {
|
if ($do_trace) {
|
if ($do_trace) {
|
print STDERR "--- use \${$para} -> $para_tbl{$para}\n";
|
print STDERR "--- use \${$para} -> $para_tbl{$para}\n";
|
} else {
|
} else {
|
## print STDERR "%vbomconv-I: \${$para} -> $para_tbl{$para}\n";
|
## print STDERR "vbomconv-I: \${$para} -> $para_tbl{$para}\n";
|
}
|
}
|
$_ = $pre . "!" . $para_tbl{$para} . $post;
|
$_ = $pre . "!" . $para_tbl{$para} . $post;
|
} else {
|
} else {
|
print STDERR "%vbomconv-E: undefined \${$para} in $vbom_file\n";
|
print STDERR "vbomconv-E: undefined \${$para} in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
}
|
}
|
|
|
if (/^\[([a-z,]+)\]\s*(.+)$/) { # [xxx,yyy] tag seen
|
if (/^\[([a-z,]+)\]\s*(.+)$/) { # [xxx,yyy] tag seen
|
my $qual = $1;
|
my $qual = $1;
|
my $name = $2;
|
my $name = $2;
|
my $keep = $is_any;
|
my $keep = $is_any;
|
## print STDERR "+++1 |$qual|$name|$vbom|\n";
|
## print STDERR "+++1 |$qual|$name|$vbom|\n";
|
foreach my $pref (split /,/,$qual) {
|
foreach my $pref (split /,/,$qual) {
|
if ($pref =~ /^(xst|ghdl|isim|sim)$/) {
|
if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim)$/) {
|
$keep = 1 if ($pref eq "xst" && $is_xst);
|
|
$keep = 1 if ($pref eq "ghdl" && $is_ghdl);
|
$keep = 1 if ($pref eq "ghdl" && $is_ghdl);
|
|
$keep = 1 if ($pref eq "xst" && $is_xst);
|
$keep = 1 if ($pref eq "isim" && $is_isim);
|
$keep = 1 if ($pref eq "isim" && $is_isim);
|
|
$keep = 1 if ($pref eq "vsyn" && $is_vsyn);
|
|
$keep = 1 if ($pref eq "vsim" && $is_vsim);
|
$keep = 1 if ($pref eq "sim" && $is_sim);
|
$keep = 1 if ($pref eq "sim" && $is_sim);
|
} else {
|
} else {
|
print STDERR "%vbomconv-W: unknown tag [$pref] in $vbom_file\n";
|
print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n";
|
}
|
}
|
}
|
}
|
if (not $keep) {
|
if (not $keep) {
|
print STDERR "--- drop \"$_\"\n" if $do_trace;
|
print STDERR "--- drop \"$_\"\n" if $do_trace;
|
next;
|
next;
|
| Line 680... |
Line 787... |
|
|
# process @ucf_cpp: lines
|
# process @ucf_cpp: lines
|
} elsif ($tag eq '@ucf_cpp') {
|
} elsif ($tag eq '@ucf_cpp') {
|
push @ucf_cpp_list, $val;
|
push @ucf_cpp_list, $val;
|
|
|
|
# process @xdc: lines
|
|
} elsif ($tag eq '@xdc') {
|
|
push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val);
|
|
|
# process @lib: lines
|
# process @lib: lines
|
} elsif ($tag eq '@lib') {
|
} elsif ($tag eq '@lib') {
|
if ($val eq 'unisim') {
|
if ($val eq 'unisim') {
|
$has_unisim = 1;
|
$has_unisim = 1;
|
|
} elsif ($val eq 'unimacro') {
|
|
$has_unimacro = 1;
|
} elsif ($val eq 'simprim') {
|
} elsif ($val eq 'simprim') {
|
$has_simprim = 1;
|
$has_simprim = 1;
|
} else {
|
} else {
|
print STDERR "%vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
|
|
|
# catch invalid @ tags
|
} else {
|
} else {
|
print STDERR "%vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
|
print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
next;
|
next;
|
}
|
}
|
|
|
| Line 718... |
Line 833... |
}
|
}
|
if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd
|
if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd
|
$has_simprim = 1;
|
$has_simprim = 1;
|
}
|
}
|
|
|
|
|
# build vbom table
|
# build vbom table
|
push @{$vbom_tbl{$vbom}}, $fullname;
|
push @{$vbom_files{$vbom}}, $fullname;
|
print STDERR "--- add $fullname\n" if $do_trace;
|
print STDERR "--- add $fullname\n" if $do_trace;
|
|
|
# if a vbom, queue if not not already read
|
# if a vbom, queue if not not already read
|
if ($fullname =~ m{\.vbom$} && not exists $read_tbl{$fullname} ) {
|
if ($fullname =~ m{\.vbom$} && not exists $vbom_done{$fullname} ) {
|
push @vbom_list, $fullname;
|
push @vbom_queue, $fullname;
|
print STDERR "--- queue $fullname\n" if $do_trace;
|
print STDERR "--- queue $fullname\n" if $do_trace;
|
}
|
}
|
|
|
}
|
}
|
|
|
| Line 742... |
Line 856... |
|
|
sub scan_vbom {
|
sub scan_vbom {
|
my ($vbom) = @_;
|
my ($vbom) = @_;
|
|
|
$level += 1;
|
$level += 1;
|
my $rank = 1000*$level + scalar(@{$vbom_tbl{$vbom}});
|
my $rank = 1000*$level + scalar(@{$vbom_files{$vbom}});
|
print STDERR "--> $level: $vbom\n" if $do_trace;
|
print STDERR "--> $level: $vbom\n" if $do_trace;
|
|
|
die "%vbomcov-E excessive vbom stack depth \n" if $level>=1000;
|
die "vbomcov-E excessive vbom stack depth \n" if $level>=1000;
|
|
|
|
if (exists $vbom_rank{$vbom}) {
|
|
$vbom_rank{$vbom}{min} = $level if $level < $vbom_rank{$vbom}{min};
|
|
$vbom_rank{$vbom}{max} = $level if $level > $vbom_rank{$vbom}{max};
|
|
} else {
|
|
$vbom_rank{$vbom} = {min=>$level, max=>$level};
|
|
}
|
|
|
foreach (@{$vbom_tbl{$vbom}}) {
|
foreach (@{$vbom_files{$vbom}}) {
|
my $file = $_;
|
my $file = $_;
|
$rank -= 1;
|
$rank -= 1;
|
if (m{\.vbom$}) {
|
if (m{\.vbom$}) {
|
scan_vbom($file);
|
scan_vbom($file);
|
} else {
|
} else {
|
if (exists $file_tbl{$file}) {
|
if (exists $srcfile_rank{$file}) {
|
if ($rank > $file_tbl{$file}) {
|
if ($rank > $srcfile_rank{$file}) {
|
print STDERR " $file $file_tbl{$file} -> $rank\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} -> $rank\n" if $do_trace;
|
$file_tbl{$file} = $rank;
|
$srcfile_rank{$file} = $rank;
|
} else {
|
} else {
|
print STDERR " $file $file_tbl{$file} (keep)\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} (keep)\n" if $do_trace;
|
}
|
}
|
} else {
|
} else {
|
$file_tbl{$file} = $rank;
|
$srcfile_rank{$file} = $rank;
|
print STDERR " $file $file_tbl{$file} (new)\n" if $do_trace;
|
print STDERR " $file $srcfile_rank{$file} (new)\n" if $do_trace;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
print STDERR "<-- $level: $vbom\n" if $do_trace;
|
print STDERR "<-- $level: $vbom\n" if $do_trace;
|
| Line 785... |
Line 906... |
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
|
|
sub write_vbomdep {
|
sub write_vbomdep {
|
my ($target) = @_;
|
my ($target) = @_;
|
print "#\n";
|
print "#\n";
|
print "# .dep_ on .vbom dependencies\n";
|
print "# .dep_* on .vbom dependencies\n";
|
print "#\n";
|
print "#\n";
|
foreach (sort keys %read_tbl) {
|
foreach (sort keys %vbom_done) {
|
print "$target : $_\n";
|
print "$target : $_\n";
|
}
|
}
|
}
|
}
|
|
|
#-------------------------------------------------------------------------------
|
#-------------------------------------------------------------------------------
|
| Line 819... |
Line 940... |
|
|
sub print_help {
|
sub print_help {
|
print "usage: vbomconf file.vbom\n";
|
print "usage: vbomconf file.vbom\n";
|
print " --help this message\n";
|
print " --help this message\n";
|
print " --trace trace recursive processing of vbom's\n";
|
print " --trace trace recursive processing of vbom's\n";
|
print " --dep_xst generate xst dependencies for make (on stdout)\n";
|
print " --dep_ghdl generate ghdl dependencies for make\n";
|
print " --dep_ghdl generate ghdl dependencies for make (on stdout)\n";
|
print " --dep_xst generate xst dependencies for make\n";
|
print " --dep_isim generate isim dependencies for make (on stdout)\n";
|
print " --dep_isim generate isim dependencies for make\n";
|
print " --xst_prj generate xst project file (on stdout)\n";
|
print " --dep_vsyn generate vsyn dependencies for make\n";
|
print " --isim_prj generate isim project file (on stdout)\n";
|
|
print " --viv_vhdl generate vivado read_vhdl command (on stdout)\n";
|
|
print " --ghdl_a generate and execute ghdl -a (analyse)\n";
|
print " --ghdl_a generate and execute ghdl -a (analyse)\n";
|
print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n";
|
print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n";
|
print " --ghdl_i generate and execute ghdl -i (inspect)\n";
|
print " --ghdl_i generate and execute ghdl -i (inspect)\n";
|
print " --ghdl_i_cmd like ghdl_i, but only print command, no exec\n";
|
print " --ghdl_i_cmd like ghdl_i, but only print command, no exec\n";
|
print " --ghdl_m generate and execute ghdl -m (make)\n";
|
print " --ghdl_m generate and execute ghdl -m (make)\n";
|
print " --ghdl_m_cmd like ghdl_m, but only print command, no exec\n";
|
print " --ghdl_m_cmd like ghdl_m, but only print command, no exec\n";
|
print " --xst_export=s export all xst source files into directory s\n";
|
print " --xst_prj generate xst project file\n";
|
|
print " --isim_prj generate isim project file\n";
|
|
print " --vsyn_prj generate vivado synthesis project definition\n";
|
print " --ghdl_export=s export all ghdl source files into directory s\n";
|
print " --ghdl_export=s export all ghdl source files into directory s\n";
|
|
print " --xst_export=s export all xst source files into directory s\n";
|
print " --isim_export=s export all isim source files into directory s\n";
|
print " --isim_export=s export all isim source files into directory s\n";
|
print " --get_top return top level entity name\n";
|
print " --get_top return top level entity name\n";
|
print " --flist list all files touched by vbom for all tags\n";
|
print " --flist list all files touched by vbom for all tags\n";
|
}
|
}
|
