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one transaction clock at a sustained or pipelined rate.  This
one transaction clock at a sustained or pipelined rate.  This
[bus translator](rtl/wbm2axisp.v) is designed to be able to handle one
[bus translator](rtl/wbm2axisp.v) is designed to be able to handle one
transaction per clock (pipelined), although [(due to Xilinx's MIG design)
transaction per clock (pipelined), although [(due to Xilinx's MIG design)
the delay may be up to 27 clocks](http://opencores.org/project,wbddr3).  (Ouch!)
the delay may be up to 27 clocks](http://opencores.org/project,wbddr3).  (Ouch!)
 
 
 
Since the initial build of the core, I've added the
 
[WB to AXI lite](rtl/wbm2axilite.v) bridge.  This is also a pipelined bridge,
 
and like the original one it is also formally verified.
 
 
# AXI to Wishbone conversion
# AXI to Wishbone conversion
 
 
Since the project began, a full-fledged [AXI4 to Wishbone bridge](rtl/axim2wbsp.v) has been added to the project.
As of 20181228, the project now contains an
This converter handles synchronizing the write channels, turning AXI read/write
[AXI4 lite read channel to wishbone interface](rtl/axilrd2wbsp.v), and also an
requests into pipeline wishbone requests, maintaining the AXI ID fields, etc.
[AXI4 lite write channel to wishbone interface](rtl/axilwr2wbsp.v).
It ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS fields.  It supports
A third core, the [AXI-lite to WB core](rtl/axlite2wbsp.v) combines these
xBURST types of FIXED (2'b00) and INCR (2'b01), but not WRAP (2'b10) or
two together using a  [Wishbone arbiter](rtl/wbartbiter.v).  All four of these
reserved (2'b11).  It does not (yet) support bridging between busses of
designs have been formally verified, and should be reliable to use.
different widths, so both the AXI and the WB bus must have the same width.
 
 
As of 20190101, [this AXI-lite to WB bridge](rtl/axlite2wbsp.v) has been
AXI4 is a complicated protocol, however, especially when
FPGA proven.
[compared to WB](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html).
 
 
The full AXI4 protocol, however, is rather complicated--especially when
_Finally, whereas the [bridge](rtl/axim2wbsp.v) has been written, it has yet
[compared to WB](http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html).  As a
to be significantly tested or formally proven.  If you are interested in
result, while there is a full-fledged
helping to test it, please contact me at (zipcpu (at) gmail.com).  Until
[AXI4 to Wishbone bridge](rtl/axim2wbsp.v) within this project,
that time, it must be said that the result is subject to change._
this bridge is still not ready for prime time.  It is designed to
 
synchronize the write channels, turning AXI read/write requests into pipeline
 
wishbone requests, maintaining the AXI ID fields, handle burst transactions,
 
etc.  As designed, it ignores the AXI xSIZE, xLOCK, xCACHE, xPROT, and xQOS
 
fields, while supporting xBURST types of FIXED (2'b00) and INCR (2'b01)
 
but not WRAP (2'b10) or reserved (2'b11).  The design supports bridging
 
between busses of different widths.  The only problem is ...
 
this full AXI4 to WB converter _doesn't work_ (yet).  I know this because it
 
doesn't yet pass formal verification.
 
 
# Formal Verification
# Formal Verification
 
 
This particular version of the tools includes an initial attempt at
 
formally proving that the core(s) work.
 
 
 
Currently, the project contains formal specifications for
Currently, the project contains formal specifications for
[Avalon](bench/formal/fav_slave.v), [Wishbone](bench/formal/fwb_slave.v), and
[Avalon](bench/formal/fav_slave.v), [Wishbone](bench/formal/fwb_slave.v), and
[AXI](bench/formal/faxi_slave.v) busses.  Components with working proofs
[AXI](bench/formal/faxi_slave.v) busses.
include the [WB to AXI](rtl/wbm2axisp.v) bridge as well as the
 
[WB arbiter](rtl/wbarbiter.v) needed for the [AXI to WB](rtl/axim2wbsp.v).
 
I also have a working proof for an Avalon to WB bridge that isn't posted
 
here.
 
 
 
The [AXI4 to Wishbone bridge](rtl/axim2wbsp.v) remains a work in progress
 
that isn't getting a lot of attention.
 
 
 
# Commercial Applications
# Commercial Applications
 
 
Should you find the GPLv3 license insufficient for your needs, other licenses
Should you find the GPLv3 license insufficient for your needs, other licenses
can be purchased from Gisselquist Technology, LLc.
can be purchased from Gisselquist Technology, LLc.
 
 
# Thanks
# Thanks
 
 
I'd like to thank @wallento for his initial work on a
I'd like to thank @wallento for his initial work on a
[Wishbone to AXI converter](https://github.com/wallento/wb2axi), and his
[Wishbone to AXI converter](https://github.com/wallento/wb2axi), and his
encouragement to improve upon it.  While this isn't a fork of his work, it
encouragement to improve upon it.  While this isn't a fork of his work, the
takes its motivation from his work.
[pipelined wishbone to AXI bridge](rtl/wbm2axisp.v) took its initial
 
motivation from his work.

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