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`error This full featured AXI to WB converter does not (yet) work
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: aximwr2wbsp.v
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// Filename: aximwr2wbsp.v
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//
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//
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// Project: Pipelined Wishbone to AXI converter
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// Project: Pipelined Wishbone to AXI converter
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// Purpose: Convert the three AXI4 write channels to a single wishbone
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// Purpose: Convert the three AXI4 write channels to a single wishbone
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// channel to write the results.
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// channel to write the results.
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//
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//
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// Still need to implement the lock feature.
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// Still need to implement the lock feature.
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//
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//
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// We're going to need to keep track of transaction bursts in progress,
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// since the wishbone doesn't. For this, we'll use a FIFO, but with
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// multiple pointers:
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//
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// fifo_ahead - pointer to where to write the next incoming
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// bus request .. adjusted when
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// (o_axi_awready)&&(i_axi_awvalid)
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// fifo_neck - pointer to where to read from the FIFO in
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// order to issue another request. Used
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// when (o_wb_stb)&&(!i_wb_stall)
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// fifo_torso - pointer to where to write a wishbone
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// transaction upon return.
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// when (i_ack)
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// fifo_tail - pointer to where the last transaction is to
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// be retired when
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// (i_axi_rvalid)&&(i_axi_rready)
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//
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// All of these are to be set to zero upon a reset signal.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This file is part of the pipelined Wishbone to AXI converter project, a
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// modify it under the terms of the GNU General Public License as published
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// project that contains multiple bus bridging designs and formal bus property
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// by the Free Software Foundation, either version 3 of the License, or (at
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// sets.
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// your option) any later version.
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//
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//
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// The bus bridge designs and property sets are free RTL designs: you can
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// redistribute them and/or modify any of them under the terms of the GNU
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// Lesser General Public License as published by the Free Software Foundation,
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// either version 3 of the License, or (at your option) any later version.
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// for more details.
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//
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//
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// The bus bridge designs and property sets are distributed in the hope that
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// You should have received a copy of the GNU General Public License along
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// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// target there if the PDF file isn't present.) If not, see
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// GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with these designs. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/lgpl.html
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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`default_nettype none
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| Line 86... |
Line 110... |
output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel,
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output wire [(C_AXI_DATA_WIDTH/8-1):0] o_wb_sel,
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input wire i_wb_ack,
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input wire i_wb_ack,
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input wire i_wb_stall,
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input wire i_wb_stall,
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// input [(C_AXI_DATA_WIDTH-1):0] i_wb_data,
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// input [(C_AXI_DATA_WIDTH-1):0] i_wb_data,
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input wire i_wb_err
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input wire i_wb_err
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`ifdef FORMAL
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,
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output wire [LGFIFO-1:0] f_fifo_ahead,
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output wire [LGFIFO-1:0] f_fifo_dhead,
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output wire [LGFIFO-1:0] f_fifo_neck,
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output wire [LGFIFO-1:0] f_fifo_torso,
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output wire [LGFIFO-1:0] f_fifo_tail
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`endif
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);
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);
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localparam DW = C_AXI_DATA_WIDTH;
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localparam DW = C_AXI_DATA_WIDTH;
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wire w_reset;
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wire w_reset;
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| Line 119... |
Line 151... |
reg filling_fifo, incr;
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reg filling_fifo, incr;
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reg [7:0] len;
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reg [7:0] len;
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reg [(AW-1):0] wr_fifo_addr;
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reg [(AW-1):0] wr_fifo_addr;
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reg [(C_AXI_ID_WIDTH-1):0] wr_fifo_id;
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reg [(C_AXI_ID_WIDTH-1):0] wr_fifo_id;
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wire axi_aw_req, axi_wr_req;
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wire axi_aw_req, axi_wr_req, axi_wr_ack;
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assign axi_aw_req = (o_axi_awready)&&(i_axi_awvalid);
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assign axi_aw_req = (o_axi_awready)&&(i_axi_awvalid);
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assign axi_wr_req = (o_axi_wready)&&(i_axi_wvalid);
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assign axi_wr_req = (o_axi_wready)&&(i_axi_wvalid);
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assign axi_wr_ack = (o_axi_bvalid)&&(i_axi_bready);
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wire fifo_full;
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wire fifo_full;
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assign fifo_full = (next_ahead == fifo_tail)||(next_dhead ==fifo_tail);
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assign fifo_full = (next_ahead == fifo_tail)||(next_dhead ==fifo_tail);
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initial fifo_ahead = 0;
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initial fifo_ahead = 0;
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| Line 197... |
Line 230... |
err_state <= 0;
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err_state <= 0;
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end else if (o_wb_stb)
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end else if (o_wb_stb)
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begin
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begin
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if (i_wb_err)
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if (i_wb_err)
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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err_state <= 1'b0;
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err_state <= 1'b1;
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end
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end else if (!i_wb_stall)
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else if (!i_wb_stall)
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o_wb_stb <= (fifo_ahead != next_neck)
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o_wb_stb <= (fifo_ahead != next_neck)
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&&(fifo_dhead != next_neck);
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&&(fifo_dhead != next_neck);
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if ((!i_wb_stall)&&(fifo_neck != fifo_ahead)&&(fifo_neck != fifo_dhead))
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if ((!i_wb_stall)&&(fifo_neck != fifo_ahead)&&(fifo_neck != fifo_dhead))
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fifo_neck <= next_neck;
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fifo_neck <= next_neck;
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| Line 212... |
Line 245... |
if (i_wb_ack)
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if (i_wb_ack)
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fifo_torso <= next_torso;
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fifo_torso <= next_torso;
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if (fifo_neck == next_torso)
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if (fifo_neck == next_torso)
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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end else if (err_state)
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end else if ((err_state)||(i_wb_err))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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if (fifo_torso != fifo_neck)
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o_wb_stb <= 1'b0;
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err_state <= (err_state)||(i_wb_err);
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if ((o_wb_cyc)&&(fifo_torso != fifo_neck))
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fifo_torso <= next_torso;
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fifo_torso <= next_torso;
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if (fifo_neck == next_torso)
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if (fifo_neck == next_torso)
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err_state <= 1'b0;
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err_state <= 1'b0;
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end else if (o_wb_cyc)
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end else if (o_wb_cyc)
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begin
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begin
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if (i_wb_ack)
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if (i_wb_ack)
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fifo_torso <= next_torso;
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fifo_torso <= next_torso;
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if (fifo_neck == next_torso)
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if (fifo_neck == next_torso)
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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end else if((fifo_ahead!= fifo_neck)&&(fifo_dhead != fifo_neck))
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end else if((fifo_ahead!= fifo_neck)
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&&(fifo_dhead != fifo_neck))
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begin
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begin
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o_wb_cyc <= 1;
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o_wb_cyc <= 1;
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o_wb_stb <= 1;
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o_wb_stb <= 1;
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end
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end
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end
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end
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| Line 252... |
Line 288... |
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initial fifo_tail = 0;
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initial fifo_tail = 0;
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always @(posedge i_axi_clk)
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always @(posedge i_axi_clk)
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if (w_reset)
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if (w_reset)
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fifo_tail <= 0;
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fifo_tail <= 0;
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else if ((o_axi_bvalid)&&(i_axi_bready))
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else if (axi_wr_ack)
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fifo_tail <= next_tail;
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fifo_tail <= next_tail;
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always @(posedge i_axi_clk)
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always @(posedge i_axi_clk)
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afifo_at_tail <= afifo[fifo_tail];
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afifo_at_tail <= afifo[fifo_tail];
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always @(posedge i_axi_clk)
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always @(posedge i_axi_clk)
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| Line 308... |
Line 344... |
assert(f_fifo_torso_used <= f_dfifo_used);
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assert(f_fifo_torso_used <= f_dfifo_used);
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always @(*)
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always @(*)
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assert((!o_wb_stb)||
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assert((!o_wb_stb)||
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((fifo_neck != fifo_ahead)
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((fifo_neck != fifo_ahead)
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&&(fifo_neck != fifo_dhead)));
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&&(fifo_neck != fifo_dhead)));
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assign f_fifo_ahead = fifo_ahead;
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assign f_fifo_dhead = fifo_dhead;
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assign f_fifo_neck = fifo_neck;
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assign f_fifo_torso = fifo_torso;
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assign f_fifo_tail = fifo_tail;
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always @(*)
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if (i_axi_awvalid)
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assert(!i_axi_awburst[1]);
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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