| Line 163... |
Line 163... |
assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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reg wb_mid_cycle, wb_last_cyc_stb, wb_mid_abort, wb_cyc_stb;
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reg wb_mid_cycle, wb_mid_abort;
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wire wb_abort;
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wire wb_abort;
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// Command logic
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// Command logic
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// Transaction ID logic
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// Transaction ID logic
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wire [(LGFIFOLN-1):0] fifo_head;
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wire [(LGFIFOLN-1):0] fifo_head;
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| Line 582... |
Line 582... |
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//
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//
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// Wishbone abort logic
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// Wishbone abort logic
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//
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//
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// Did we just accept something?
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initial wb_cyc_stb = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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wb_cyc_stb <= 1'b0;
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else
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wb_cyc_stb <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
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// Else, are we mid-cycle?
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// Else, are we mid-cycle?
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initial wb_mid_cycle = 0;
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initial wb_mid_cycle = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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wb_mid_cycle <= 0;
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wb_mid_cycle <= 0;
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| Line 623... |
Line 615... |
(w_fifo_full)||(wb_mid_abort)
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(w_fifo_full)||(wb_mid_abort)
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||((o_axi_awvalid)&&(!i_axi_awready))
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||((o_axi_awvalid)&&(!i_axi_awready))
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||((o_axi_wvalid )&&(!i_axi_wready ))
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||((o_axi_wvalid )&&(!i_axi_wready ))
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||((o_axi_arvalid)&&(!i_axi_arready)));
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||((o_axi_arvalid)&&(!i_axi_arready)));
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// Make Verilator happy
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// verilator lint_off UNUSED
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wire [2:0] unused;
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assign unused = { i_axi_bresp[0], i_axi_rresp[0], i_axi_rlast };
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// verilator lint_on UNUSED
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/////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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//
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