| Line 62... |
Line 62... |
) (
|
) (
|
input i_clk, // System clock
|
input i_clk, // System clock
|
input i_reset,// Wishbone reset signal
|
input i_reset,// Wishbone reset signal
|
|
|
// AXI write address channel signals
|
// AXI write address channel signals
|
input i_axi_wready, // Slave is ready to accept
|
input i_axi_awready, // Slave is ready to accept
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wid, // Write ID
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
|
output reg [AW-1:0] o_axi_waddr, // Write address
|
output reg [AW-1:0] o_axi_awaddr, // Write address
|
output wire [7:0] o_axi_wlen, // Write Burst Length
|
output wire [7:0] o_axi_awlen, // Write Burst Length
|
output wire [2:0] o_axi_wsize, // Write Burst size
|
output wire [2:0] o_axi_awsize, // Write Burst size
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output wire [1:0] o_axi_wburst, // Write Burst type
|
output wire [1:0] o_axi_awburst, // Write Burst type
|
output wire [1:0] o_axi_wlock, // Write lock type
|
output wire [1:0] o_axi_awlock, // Write lock type
|
output wire [3:0] o_axi_wcache, // Write Cache type
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output wire [3:0] o_axi_awcache, // Write Cache type
|
output wire [2:0] o_axi_wprot, // Write Protection type
|
output wire [2:0] o_axi_awprot, // Write Protection type
|
output reg o_axi_wvalid, // Write address valid
|
output wire [3:0] o_axi_awqos, // Write Quality of Svc
|
|
output reg o_axi_awvalid, // Write address valid
|
|
|
// AXI write data channel signals
|
// AXI write data channel signals
|
input i_axi_wd_wready, // Write data ready
|
input i_axi_wready, // Write data ready
|
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
|
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data
|
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data
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output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes
|
output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes
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output wire o_axi_wlast, // Last write transaction
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output wire o_axi_wd_last, // Last write transaction
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output reg o_axi_wvalid, // Write valid
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output reg o_axi_wd_valid, // Write valid
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|
|
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// AXI write response channel signals
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// AXI write response channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
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input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID
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input [1:0] i_axi_wd_bresp, // Write response
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input [1:0] i_axi_bresp, // Write response
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input i_axi_wd_bvalid, // Write reponse valid
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input i_axi_bvalid, // Write reponse valid
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output wire o_axi_wd_bready, // Response ready
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output wire o_axi_bready, // Response ready
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|
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// AXI read address channel signals
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// AXI read address channel signals
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input i_axi_rready, // Read address ready
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input i_axi_arready, // Read address ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_rid, // Read ID
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
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output wire [AW-1:0] o_axi_raddr, // Read address
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output wire [AW-1:0] o_axi_araddr, // Read address
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output wire [7:0] o_axi_rlen, // Read Burst Length
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output wire [7:0] o_axi_arlen, // Read Burst Length
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output wire [2:0] o_axi_rsize, // Read Burst size
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output wire [2:0] o_axi_arsize, // Read Burst size
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output wire [1:0] o_axi_rburst, // Read Burst type
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output wire [1:0] o_axi_arburst, // Read Burst type
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output wire [1:0] o_axi_rlock, // Read lock type
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output wire [1:0] o_axi_arlock, // Read lock type
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output wire [3:0] o_axi_rcache, // Read Cache type
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output wire [3:0] o_axi_arcache, // Read Cache type
|
output wire [2:0] o_axi_rprot, // Read Protection type
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output wire [2:0] o_axi_arprot, // Read Protection type
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output reg o_axi_rvalid, // Read address valid
|
output wire [3:0] o_axi_arqos, // Read Protection type
|
|
output reg o_axi_arvalid, // Read address valid
|
|
|
// AXI read data channel signals
|
// AXI read data channel signals
|
input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
|
input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID
|
input [1:0] i_axi_rd_rresp, // Read response
|
input [1:0] i_axi_rresp, // Read response
|
input i_axi_rd_rvalid, // Read reponse valid
|
input i_axi_rvalid, // Read reponse valid
|
input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data
|
input [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data
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input i_axi_rd_last, // Read last
|
input i_axi_rlast, // Read last
|
output wire o_axi_rd_rready, // Read Response ready
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output wire o_axi_rready, // Read Response ready
|
|
|
// We'll share the clock and the reset
|
// We'll share the clock and the reset
|
input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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input i_wb_we,
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input i_wb_we,
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| Line 160... |
Line 161... |
reg cmptd_one_wr;
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reg cmptd_one_wr;
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reg cmptd_one_rd;
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reg cmptd_one_rd;
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|
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|
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// Things we're not changing ...
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// Things we're not changing ...
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assign o_axi_wlen = 8'h0; // Burst length is one
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assign o_axi_awlen = 8'h0; // Burst length is one
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assign o_axi_wsize = 3'b101; // maximum bytes per burst is 32
|
assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_wburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_rburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_wlock = 2'b00; // Normal signaling
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assign o_axi_awlock = 2'b00; // Normal signaling
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assign o_axi_rlock = 2'b00; // Normal signaling
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assign o_axi_arlock = 2'b00; // Normal signaling
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assign o_axi_wcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_rcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_wprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_awprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_rprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'h010; // Unpriviledged, unsecure, data access
|
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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|
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// Command logic
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// Command logic
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assign o_wb_stall = (i_wb_we)&&(~i_axi_wready)
|
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||(~i_wb_we)&&(!i_axi_rready);
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// Write address logic
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// Write address logic
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|
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_wvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
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||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
|
if (!o_wb_stall)
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o_axi_waddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
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o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
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|
|
reg [5:0] transaction_id;
|
reg [5:0] transaction_id;
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
if (!i_wb_cyc)
|
if (!i_wb_cyc)
|
transaction_id <= 6'h00;
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transaction_id <= 6'h00;
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else if ((i_wb_stb)&&(~o_wb_stall))
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else if ((i_wb_stb)&&(~o_wb_stall))
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transaction_id <= transaction_id + 6'h01;
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transaction_id <= transaction_id + 6'h01;
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assign o_axi_wid = transaction_id;
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assign o_axi_awid = transaction_id;
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|
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// Read address logic
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// Read address logic
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assign o_axi_rid = transaction_id;
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assign o_axi_arid = transaction_id;
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assign o_axi_raddr = o_axi_waddr;
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assign o_axi_araddr = o_axi_awaddr;
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assign o_axi_rlen = o_axi_wlen;
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assign o_axi_arlen = o_axi_awlen;
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assign o_axi_rsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
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always @(posedge i_clk)
|
always @(posedge i_clk)
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o_axi_rvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
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||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);
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|
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|
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// Write data logic
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// Write data logic
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assign o_axi_wd_wid = transaction_id;
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|
|
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generate
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generate
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if (DW == 32)
|
if (DW == 32)
|
begin
|
begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
|
if (!o_wb_stall)
|
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
|
case(i_wb_addr[1:0])
|
case(i_wb_addr[1:0])
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b01:o_axi_wstrb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b10:o_axi_wstrb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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2'b11:o_axi_wstrb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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endcase
|
endcase
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end else if (DW == 128)
|
end else if (DW == 128)
|
begin
|
begin
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (!o_wb_stall)
|
if (!o_wb_stall)
|
o_axi_wd_data <= i_wb_data;
|
o_axi_wdata <= i_wb_data;
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always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (!o_wb_stall)
|
if (!o_wb_stall)
|
o_axi_wd_strb <= i_wb_sel;
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o_axi_wstrb <= i_wb_sel;
|
end endgenerate
|
end endgenerate
|
|
|
assign o_axi_wd_last = 1'b1;
|
assign o_axi_wlast = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
|
o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
|
||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
|
||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
|
|
|
// Read data channel / response logic
|
// Read data channel / response logic
|
assign o_axi_rd_rready = 1'b1;
|
assign o_axi_rready = 1'b1;
|
assign o_axi_wd_bready = 1'b1;
|
assign o_axi_bready = 1'b1;
|
|
|
wire w_fifo_full;
|
wire w_fifo_full;
|
generate
|
generate
|
if (STRICT_ORDER == 0)
|
if (STRICT_ORDER == 0)
|
begin
|
begin
|
| Line 261... |
Line 260... |
reg [1:0] low_addr;
|
reg [1:0] low_addr;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_wb_stb)&&(!o_wb_stall))
|
if ((i_wb_stb)&&(!o_wb_stall))
|
low_addr <= i_wb_addr[1:0];
|
low_addr <= i_wb_addr[1:0];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((o_axi_rvalid)&&(i_axi_rready))
|
if ((o_axi_arvalid)&&(i_axi_arready))
|
reorder_fifo_addr[o_axi_rid] <= low_addr;
|
reorder_fifo_addr[o_axi_arid] <= low_addr;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(reorder_fifo_addr[1:0])
|
case(reorder_fifo_addr[1:0])
|
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
|
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
|
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
|
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
|
| Line 291... |
Line 290... |
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
|
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
|
assign n_fifo_head = fifo_head+1'b1;
|
assign n_fifo_head = fifo_head+1'b1;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
if ((i_axi_rvalid)&&(o_axi_rready))
|
reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
|
reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
|
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
if ((i_axi_rvalid)&&(o_axi_rready))
|
begin
|
begin
|
reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
|
reorder_fifo_valid[i_axi_rid] <= 1'b1;
|
reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
|
reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];
|
end
|
end
|
if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
|
if ((i_axi_bvalid)&&(o_axi_bready))
|
begin
|
begin
|
reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
|
reorder_fifo_valid[i_axi_bid] <= 1'b1;
|
reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
|
reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];
|
end
|
end
|
|
|
if (reorder_fifo_valid[fifo_tail])
|
if (reorder_fifo_valid[fifo_tail])
|
begin
|
begin
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
| Line 345... |
Line 344... |
end
|
end
|
assign w_fifo_full = r_fifo_full;
|
assign w_fifo_full = r_fifo_full;
|
end else begin
|
end else begin
|
assign w_fifo_full = 1'b0;
|
assign w_fifo_full = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_data <= i_axi_rd_data;
|
o_wb_data <= i_axi_rdata;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
|
o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready))
|
||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
|
||((i_axi_bvalid)&&(o_axi_bready));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
|
o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
|
||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
|
||((i_axi_rvalid)&&(i_axi_rresp[1]))
|
||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
|
||((i_axi_bvalid)&&(i_axi_bresp[1])));
|
end endgenerate
|
end endgenerate
|
|
|
|
|
// Now, the difficult signal ... the stall signal
|
// Now, the difficult signal ... the stall signal
|
// Let's build for a single cycle input ... and only stall if something
|
// Let's build for a single cycle input ... and only stall if something
|
// outgoing is valid and nothing is ready.
|
// outgoing is valid and nothing is ready.
|
assign o_wb_stall = (i_wb_cyc)&&(
|
assign o_wb_stall = (i_wb_cyc)&&(
|
(w_fifo_full)
|
(w_fifo_full)
|
|
||((o_axi_awvalid)&&(!i_axi_awready))
|
||((o_axi_wvalid)&&(!i_axi_wready))
|
||((o_axi_wvalid)&&(!i_axi_wready))
|
||((o_axi_wd_valid)&&(!i_axi_wd_wready))
|
||((o_axi_arvalid)&&(!i_axi_arready)));
|
||((o_axi_rvalid)&&(!i_axi_rready)));
|
|
endmodule
|
endmodule
|
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