| Line 54... |
Line 54... |
//
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//
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module wbm2axisp #(
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module wbm2axisp #(
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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// This is an int between 1-16
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter AW = 28, // Wishbone address width
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parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
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parameter DW = 128, // Wishbone data width
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parameter DW = 32, // Wishbone data width
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parameter AW = 26, // Wishbone address width
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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) (
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) (
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input i_clk, // System clock
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input i_clk, // System clock
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input i_reset,// Wishbone reset signal
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// input i_reset,// Wishbone reset signal--unused
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// AXI write address channel signals
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// AXI write address channel signals
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input i_axi_awready, // Slave is ready to accept
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input i_axi_awready, // Slave is ready to accept
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
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output reg [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
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output reg [AW-1:0] o_axi_awaddr, // Write address
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output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address
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output wire [7:0] o_axi_awlen, // Write Burst Length
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output wire [7:0] o_axi_awlen, // Write Burst Length
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output wire [2:0] o_axi_awsize, // Write Burst size
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output wire [2:0] o_axi_awsize, // Write Burst size
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output wire [1:0] o_axi_awburst, // Write Burst type
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output wire [1:0] o_axi_awburst, // Write Burst type
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output wire [1:0] o_axi_awlock, // Write lock type
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output wire [0:0] o_axi_awlock, // Write lock type
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output wire [3:0] o_axi_awcache, // Write Cache type
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output wire [3:0] o_axi_awcache, // Write Cache type
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output wire [2:0] o_axi_awprot, // Write Protection type
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output wire [2:0] o_axi_awprot, // Write Protection type
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output wire [3:0] o_axi_awqos, // Write Quality of Svc
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output wire [3:0] o_axi_awqos, // Write Quality of Svc
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output reg o_axi_awvalid, // Write address valid
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output reg o_axi_awvalid, // Write address valid
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| Line 90... |
Line 91... |
output wire o_axi_bready, // Response ready
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output wire o_axi_bready, // Response ready
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// AXI read address channel signals
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// AXI read address channel signals
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input i_axi_arready, // Read address ready
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input i_axi_arready, // Read address ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
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output wire [AW-1:0] o_axi_araddr, // Read address
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output wire [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address
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output wire [7:0] o_axi_arlen, // Read Burst Length
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output wire [7:0] o_axi_arlen, // Read Burst Length
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output wire [2:0] o_axi_arsize, // Read Burst size
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output wire [2:0] o_axi_arsize, // Read Burst size
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output wire [1:0] o_axi_arburst, // Read Burst type
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output wire [1:0] o_axi_arburst, // Read Burst type
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output wire [1:0] o_axi_arlock, // Read lock type
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output wire [0:0] o_axi_arlock, // Read lock type
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output wire [3:0] o_axi_arcache, // Read Cache type
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output wire [3:0] o_axi_arcache, // Read Cache type
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output wire [2:0] o_axi_arprot, // Read Protection type
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output wire [2:0] o_axi_arprot, // Read Protection type
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output wire [3:0] o_axi_arqos, // Read Protection type
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output wire [3:0] o_axi_arqos, // Read Protection type
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output reg o_axi_arvalid, // Read address valid
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output reg o_axi_arvalid, // Read address valid
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| Line 112... |
Line 113... |
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// We'll share the clock and the reset
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// We'll share the clock and the reset
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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input i_wb_we,
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input i_wb_we,
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input [AW-1:0] i_wb_addr,
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input [(AW-1):0] i_wb_addr,
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input [DW-1:0] i_wb_data,
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input [(DW-1):0] i_wb_data,
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input [(DW/8-1):0] i_wb_sel,
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input [(DW/8-1):0] i_wb_sel,
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output reg o_wb_ack,
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output reg o_wb_ack,
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output wire o_wb_stall,
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output wire o_wb_stall,
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output reg [DW-1:0] o_wb_data,
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output reg [(DW-1):0] o_wb_data,
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output reg o_wb_err
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output reg o_wb_err
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);
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);
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//*****************************************************************************
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//*****************************************************************************
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// Parameter declarations
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// Parameter declarations
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| Line 133... |
Line 134... |
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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// Internal register and wire declarations
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//*****************************************************************************
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//*****************************************************************************
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wire cmd_en;
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wire [2:0] cmd;
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wire [7:0] blen;
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wire [31:0] addr;
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wire [CTL_SIG_WIDTH-1:0] ctl;
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wire cmd_ack;
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// User interface write ports
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wire wrdata_vld;
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wire [C_AXI_DATA_WIDTH-1:0] wrdata;
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wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
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wire wrdata_cmptd;
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wire wrdata_rdy;
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wire wrdata_sts_vld;
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wire [WR_STS_WIDTH-1:0] wrdata_sts;
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// User interface read ports
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wire rddata_rdy;
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wire rddata_vld;
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wire [C_AXI_DATA_WIDTH-1:0] rddata;
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wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
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wire rddata_cmptd;
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wire [RD_STS_WIDTH-1:0] rddata_sts;
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reg cmptd_one_wr;
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reg cmptd_one_rd;
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// Things we're not changing ...
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// Things we're not changing ...
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assign o_axi_awlen = 8'h0; // Burst length is one
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assign o_axi_awlen = 8'h0; // Burst length is one
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assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_awlock = 2'b00; // Normal signaling
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assign o_axi_awlock = 1'b0; // Normal signaling
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assign o_axi_arlock = 2'b00; // Normal signaling
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assign o_axi_arlock = 1'b0; // Normal signaling
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assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_awprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'h010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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// Command logic
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// Command logic
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// Write address logic
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// Write address logic
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
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||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
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generate
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if (DW == 32)
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begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall) // 26 bit address becomes 28 bit ...
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o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
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o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall) // 28 bit address ...
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o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };
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end endgenerate
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reg [5:0] transaction_id;
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reg [5:0] transaction_id;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!i_wb_cyc)
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if (!i_wb_cyc)
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transaction_id <= 6'h00;
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transaction_id <= 6'h00;
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else if ((i_wb_stb)&&(~o_wb_stall))
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else if ((i_wb_stb)&&(~o_wb_stall))
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transaction_id <= transaction_id + 6'h01;
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transaction_id <= transaction_id + 6'h01;
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assign o_axi_awid = transaction_id;
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always @(posedge i_clk)
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if ((i_wb_stb)&&(~o_wb_stall))
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o_axi_awid <= transaction_id;
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// Read address logic
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// Read address logic
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assign o_axi_arid = transaction_id;
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assign o_axi_arid = o_axi_awid;
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assign o_axi_araddr = o_axi_awaddr;
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assign o_axi_araddr = o_axi_awaddr;
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assign o_axi_arlen = o_axi_awlen;
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assign o_axi_arlen = o_axi_awlen;
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assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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| Line 250... |
Line 236... |
reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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initial reorder_fifo_valid = 0;
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initial reorder_fifo_err = 0;
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if (DW == 32)
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if (DW == 32)
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begin
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begin
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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| Line 264... |
Line 253... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_axi_arvalid)&&(i_axi_arready))
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if ((o_axi_arvalid)&&(i_axi_arready))
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reorder_fifo_addr[o_axi_arid] <= low_addr;
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reorder_fifo_addr[o_axi_arid] <= low_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(reorder_fifo_addr[1:0])
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case(reorder_fifo_addr[fifo_tail][1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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endcase
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| Line 287... |
Line 276... |
// point to next, but let's also insist that it be LGFIFOLN
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// point to next, but let's also insist that it be LGFIFOLN
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// bits in size as well. This'll be part of the fifo_full
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// bits in size as well. This'll be part of the fifo_full
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// calculation below.
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// calculation below.
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wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
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wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
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assign n_fifo_head = fifo_head+1'b1;
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assign n_fifo_head = fifo_head+1'b1;
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assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_axi_rvalid)&&(o_axi_rready))
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if ((i_axi_rvalid)&&(o_axi_rready))
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reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
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reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
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| Line 342... |
Line 332... |
else
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else
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r_fifo_full <= (fifo_tail==n_fifo_head);
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r_fifo_full <= (fifo_tail==n_fifo_head);
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end
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end
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assign w_fifo_full = r_fifo_full;
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assign w_fifo_full = r_fifo_full;
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end else begin
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end else begin
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//
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// Strict ordering, but can only read every fourth addresses
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//
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assign w_fifo_full = 1'b0;
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assign w_fifo_full = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= i_axi_rdata;
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o_wb_data <= i_axi_rdata[31:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready))
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o_wb_ack <= (i_wb_cyc)&&(
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||((i_axi_bvalid)&&(o_axi_bready));
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((i_axi_rvalid)&&(o_axi_rready))
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||((i_axi_bvalid)&&(o_axi_bready)));
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
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o_wb_err <= (i_wb_cyc)&&((o_wb_err)
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||((i_axi_rvalid)&&(i_axi_rresp[1]))
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||((i_axi_rvalid)&&(i_axi_rresp[1]))
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||((i_axi_bvalid)&&(i_axi_bresp[1])));
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||((i_axi_bvalid)&&(i_axi_bresp[1])));
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end endgenerate
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end endgenerate
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