| Line 37... |
Line 37... |
;; version: 0.0.0
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;; version: 0.0.0
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;; changelog: - 0.0.0, initial release
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;; changelog: - 0.0.0, initial release
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;; - ...
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;; - ...
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; IMPORTANT NOTICE!
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; be carefull, if using interrupts. wishbone cycles must be atomar, as any
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; other processor local bus cycles are normally be. interrupting wishbone
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; access may cause a crash of external wishbone master fsm, especially, if
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; program flow through isr leads to another wishbone cycle!
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; wishbone variables
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NAMEREG sF , wb_addr
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NAMEREG sF , wb_addr
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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NAMEREG sE , wb_data ; also used as tmp-reg for status polling
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CONSTANT WB_ACK_FLAG , 01
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CONSTANT GPIO_IO_ADDR , 00
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CONSTANT GPIO_OE_ADDR , 01
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ADDRESS 000
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ADDRESS 000
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; main entry point
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; main entry point
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;;;;;;;;;;;;;;;;;;
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DISABLE INTERRUPT
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DISABLE INTERRUPT
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CALL gpio_init
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CALL gpio_init
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; mirroring upper nibble gpio inputs
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; mirroring upper nibble gpio inputs
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| Line 74... |
Line 66... |
SUB i , 01
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SUB i , 01
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JUMP NZ , for_i_in_4_downto_1_loop
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JUMP NZ , for_i_in_4_downto_1_loop
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CALL wb_wr
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CALL wb_wr
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JUMP mainloop
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JUMP mainloop
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; wbs_gpio module subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; usage:
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; 1. set bitmasks for output enable and output level in gpio_init subroutine
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; 2. call gpio_init subroutine to configure wbs_gpio module for operation
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; 3. use wb_wr and wb_rd subroutines to access i/o register
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; gpio start-up configuration, i. e. i/o direction and default output value
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gpio_init:
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gpio_init:
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; setting all outputs low
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; setting all outputs low
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LOAD wb_addr , GPIO_IO_ADDR
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LOAD wb_addr , GPIO_IO_ADDR
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LOAD wb_data , 00
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LOAD wb_data , 00
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CALL wb_wr
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CALL wb_wr
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| Line 85... |
Line 87... |
LOAD wb_addr , GPIO_OE_ADDR
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LOAD wb_addr , GPIO_OE_ADDR
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LOAD wb_data , 0F
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LOAD wb_data , 0F
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CALL wb_wr
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CALL wb_wr
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RETURN
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RETURN
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; register addressing
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CONSTANT GPIO_IO_ADDR , 00 ; input/output register
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CONSTANT GPIO_OE_ADDR , 01 ; output-enable register
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; wbm_picoblaze module subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
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; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
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; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
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; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
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; is a supporting subroutine, which should not be called directly
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; is a supporting subroutine, which should not be called directly
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;
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;
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; transfer principle wishbone write:
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; transfer principle wishbone write:
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| Line 116... |
Line 126... |
;
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;
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; wishbone read code =>
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; wishbone read code =>
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;
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;
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; LOAD wb_addr , ; setting up address
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; LOAD wb_addr , ; setting up address
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; CALL wb_rd ; starting wishbone read cycle
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; CALL wb_rd ; starting wishbone read cycle
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; ; wishbone cycle finished, wb_data is updated now
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; LOAD , wb_data ; wb_data is updated now
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; ; wishbone cycle finished
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; wishbone write access
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; wishbone write access
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wb_wr:
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wb_wr:
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OUTPUT wb_data , (wb_addr)
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OUTPUT wb_data , (wb_addr)
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CALL wb_wait_on_ack
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CALL wb_wait_on_ack
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| Line 137... |
Line 148... |
INPUT wb_data , (wb_addr)
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INPUT wb_data , (wb_addr)
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TEST wb_data , WB_ACK_FLAG
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TEST wb_data , WB_ACK_FLAG
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JUMP Z , wb_wait_on_ack
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JUMP Z , wb_wait_on_ack
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RETURN
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RETURN
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CONSTANT WB_ACK_FLAG , 01
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; interrupt subroutines and settings
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; IMPORTANT NOTICE!
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; be carefull, if using interrupts. wishbone cycles must be atomar, as any
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; other processor local bus cycles are normally be. interrupting wishbone
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; access may cause a crash of external wishbone master fsm, especially, if
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; program flow through isr leads to another wishbone cycle!
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; interrupt handling template, if needed
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; interrupt handling template, if needed
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isr:
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isr:
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RETURNI DISABLE
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RETURNI DISABLE
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ADDRESS 3FF
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ADDRESS 3FF
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JUMP isr
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JUMP isr
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