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[/] [wb4pb/] [trunk/] [asm/] [pbwbgpio.psm] - Diff between revs 2 and 21

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Rev 2 Rev 21
Line 37... Line 37...
;; version: 0.0.0
;; version: 0.0.0
;; changelog: - 0.0.0, initial release
;; changelog: - 0.0.0, initial release
;;            - ...
;;            - ...
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
; IMPORTANT NOTICE!
 
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
 
; other processor local bus cycles are normally be. interrupting wishbone
 
; access may cause a crash of external wishbone master fsm, especially, if
 
; program flow through isr leads to another wishbone cycle!
 
 
 
 
 
 
; wishbone variables
NAMEREG sF , wb_addr
NAMEREG sF , wb_addr
NAMEREG sE , wb_data ; also used as tmp-reg for status polling
NAMEREG sE , wb_data ; also used as tmp-reg for status polling
 
 
CONSTANT WB_ACK_FLAG , 01
 
 
 
CONSTANT GPIO_IO_ADDR , 00
 
CONSTANT GPIO_OE_ADDR , 01
 
 
 
 
 
ADDRESS 000
ADDRESS 000
 
 
; main entry point
; main entry point
 
;;;;;;;;;;;;;;;;;;
 
 
DISABLE INTERRUPT
DISABLE INTERRUPT
 
 
CALL gpio_init
CALL gpio_init
 
 
; mirroring upper nibble gpio inputs
; mirroring upper nibble gpio inputs
Line 74... Line 66...
    SUB i , 01
    SUB i , 01
    JUMP NZ , for_i_in_4_downto_1_loop
    JUMP NZ , for_i_in_4_downto_1_loop
  CALL wb_wr
  CALL wb_wr
  JUMP mainloop
  JUMP mainloop
 
 
 
 
 
; wbs_gpio module subroutines and settings
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
 
; usage:
 
; 1. set bitmasks for output enable and output level in gpio_init subroutine
 
; 2. call gpio_init subroutine to configure wbs_gpio module for operation
 
; 3. use wb_wr and wb_rd subroutines to access i/o register
 
 
 
; gpio start-up configuration, i. e. i/o direction and default output value
gpio_init:
gpio_init:
  ; setting all outputs low
  ; setting all outputs low
  LOAD wb_addr , GPIO_IO_ADDR
  LOAD wb_addr , GPIO_IO_ADDR
  LOAD wb_data , 00
  LOAD wb_data , 00
  CALL wb_wr
  CALL wb_wr
Line 85... Line 87...
  LOAD wb_addr , GPIO_OE_ADDR
  LOAD wb_addr , GPIO_OE_ADDR
  LOAD wb_data , 0F
  LOAD wb_data , 0F
  CALL wb_wr
  CALL wb_wr
RETURN
RETURN
 
 
 
; register addressing
 
CONSTANT GPIO_IO_ADDR , 00 ; input/output register
 
CONSTANT GPIO_OE_ADDR , 01 ; output-enable register
 
 
 
 
 
; wbm_picoblaze module subroutines and settings
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
; subroutines wb_wr and wb_rd are working together with external wbm_picoblaze
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
; wishbone adapter module and therefore should not be modified. wb_wait_on_ack
; is a supporting subroutine, which should not be called directly
; is a supporting subroutine, which should not be called directly
;
;
; transfer principle wishbone write:
; transfer principle wishbone write:
Line 116... Line 126...
;
;
; wishbone read code =>
; wishbone read code =>
;
;
; LOAD wb_addr ,  ; setting up address
; LOAD wb_addr ,  ; setting up address
; CALL wb_rd ; starting wishbone read cycle
; CALL wb_rd ; starting wishbone read cycle
;  ; wishbone cycle finished, wb_data is updated now
; LOAD  , wb_data ; wb_data is updated now
 
;  ; wishbone cycle finished
 
 
; wishbone write access
; wishbone write access
wb_wr:
wb_wr:
  OUTPUT wb_data , (wb_addr)
  OUTPUT wb_data , (wb_addr)
  CALL wb_wait_on_ack
  CALL wb_wait_on_ack
Line 137... Line 148...
  INPUT wb_data , (wb_addr)
  INPUT wb_data , (wb_addr)
  TEST wb_data , WB_ACK_FLAG
  TEST wb_data , WB_ACK_FLAG
  JUMP Z , wb_wait_on_ack
  JUMP Z , wb_wait_on_ack
RETURN
RETURN
 
 
 
CONSTANT WB_ACK_FLAG , 01
 
 
 
 
 
; interrupt subroutines and settings
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
 
; IMPORTANT NOTICE!
 
; be carefull, if using interrupts. wishbone cycles must be atomar, as any
 
; other processor local bus cycles are normally be. interrupting wishbone
 
; access may cause a crash of external wishbone master fsm, especially, if
 
; program flow through isr leads to another wishbone cycle!
 
 
; interrupt handling template, if needed
; interrupt handling template, if needed
isr:
isr:
RETURNI DISABLE
RETURNI DISABLE
ADDRESS 3FF
ADDRESS 3FF
JUMP isr
JUMP isr

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