URL https://opencores.org/ocsvn/wb4pb/wb4pb/trunk

Subversion Repositories wb4pb

[/] [wb4pb/] [trunk/] [sim/] [do/] [picoblaze_wb_gpio_tb.do] - Diff between revs 20 and 25

Rev 20	Rev 25
Line 41...	Line 41...
`################################################################################`	`################################################################################`

`# IMPORTANT NOTICE!`	`# IMPORTANT NOTICE!`
`# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.`	`# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.`

`# user settings: preferred hdl and working directory`	`# user settings: preferred hdl, working directory and Xilinx (R) ISE (R)`
`set wd "e:/home_users/ste.fis/projects/wb4pb/trunk/sim"`	`# installation path (needed for Verilog (R) simulation)`
	`set wd "d:/projects/wb4pb/sim"`
`set isVHDL yes`	`set isVHDL yes`
	`set XILINX_ISE_PATH "c:/xilinx/13.1"`

`# working directory cannot be changed while simulation is running`	`# working directory cannot be changed while simulation is running`
`if {![string equal -nocase [pwd] $wd]} {`	`if {![string equal -nocase [pwd] $wd]} {`
`quit -sim`	`quit -sim`
`cd $wd`	`cd $wd`
Line 76...	Line 78...
`vlog "../rtl/wbm_picoblaze.v"`	`vlog "../rtl/wbm_picoblaze.v"`
`vlog "../rtl/wbs_gpio.v"`	`vlog "../rtl/wbs_gpio.v"`
`vlog "../rtl/kcpsm3.v"`	`vlog "../rtl/kcpsm3.v"`
`vlog "../asm/pbwbgpio.v"`	`vlog "../asm/pbwbgpio.v"`
`vlog "../sim/hdl/picoblaze_wb_gpio_tb.v"`	`vlog "../sim/hdl/picoblaze_wb_gpio_tb.v"`
`vlog "$env(XILINX)/verilog/src/glbl.v"`	`vlog "${XILINX_ISE_PATH}/ise_ds/ise/verilog/src/glbl.v"`

`vsim picoblaze_wb_gpio_tb glbl`	`vsim picoblaze_wb_gpio_tb glbl`

`}`	`}`