| Line 41... |
Line 41... |
################################################################################
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################################################################################
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# IMPORTANT NOTICE!
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# IMPORTANT NOTICE!
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# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.
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# Verilog (R) simulation flow requires Xilinx (R) ISE (R) to be installed.
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# user settings: preferred hdl and working directory
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# user settings: preferred hdl, working directory and Xilinx (R) ISE (R)
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set wd "e:/home_users/ste.fis/projects/wb4pb/trunk/sim"
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# installation path (needed for Verilog (R) simulation)
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set wd "d:/projects/wb4pb/sim"
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set isVHDL yes
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set isVHDL yes
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set XILINX_ISE_PATH "c:/xilinx/13.1"
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# working directory cannot be changed while simulation is running
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# working directory cannot be changed while simulation is running
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if {![string equal -nocase [pwd] $wd]} {
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if {![string equal -nocase [pwd] $wd]} {
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quit -sim
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quit -sim
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cd $wd
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cd $wd
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| Line 86... |
Line 88... |
vlog "../rtl/kcuart_tx.v"
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vlog "../rtl/kcuart_tx.v"
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vlog "../rtl/bbfifo_16x8.v"
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vlog "../rtl/bbfifo_16x8.v"
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vlog "../rtl/kcpsm3.v"
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vlog "../rtl/kcpsm3.v"
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vlog "../asm/pbwbuart.v"
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vlog "../asm/pbwbuart.v"
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vlog "../sim/hdl/picoblaze_wb_uart_tb.v"
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vlog "../sim/hdl/picoblaze_wb_uart_tb.v"
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vlog "$env(XILINX)/verilog/src/glbl.v"
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vlog "${XILINX_ISE_PATH}/ise_ds/ise/verilog/src/glbl.v"
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vsim picoblaze_wb_uart_tb glbl
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vsim picoblaze_wb_uart_tb glbl
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}
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}
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| Line 112... |
Line 114... |
add wave -divider "WISHBONE SIGNALS"
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add wave -divider "WISHBONE SIGNALS"
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#add wave sim:/dut/wb_cyc
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#add wave sim:/dut/wb_cyc
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add wave sim:/dut/wb_stb
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add wave sim:/dut/wb_stb
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add wave sim:/dut/wb_we
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add wave sim:/dut/wb_we
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add wave -radix hex sim:/dut/wb_adr
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add wave -radix hex sim:/dut/wb_adr
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add wave -radix hex sim:/dut/wb_dat_m2s
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add wave -radix ascii sim:/dut/wb_dat_m2s
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add wave -radix hex sim:/dut/wb_dat_s2m
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add wave -radix hex sim:/dut/wb_dat_s2m
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add wave sim:/dut/wb_ack
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add wave sim:/dut/wb_ack
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}
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}
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}
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}
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