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https://opencores.org/ocsvn/wb4pb/wb4pb/trunk
[/] [wb4pb/] [trunk/] [sim/] [hdl/] [picoblaze_wb_gpio_tb.v] - Diff between revs 2 and 18
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Rev 18 |
| Line 45... |
Line 45... |
`timescale 1 ns / 1 ps
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`timescale 1 ns / 1 ps
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module picoblaze_wb_gpio_tb;
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module picoblaze_wb_gpio_tb;
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reg rst;
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reg rst_n;
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reg clk;
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reg clk;
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wire[7:0] gpio;
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wire[7:0] gpio;
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parameter PERIOD = 20;
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parameter PERIOD = 20;
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reg[7:4] test_data_in;
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reg[7:4] test_data_in;
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// system signal generation
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initial begin
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initial begin
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test_data_in = 4'h0;
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test_data_in = 4'h0;
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clk = 1'b1;
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clk = 1'b1;
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rst = 1'b1;
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rst_n = 1'b0;
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#(PERIOD*2) rst = 1'b0;
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#(PERIOD*2) rst_n = 1'b1;
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end
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end
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always #(PERIOD/2) clk = ! clk;
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always #(PERIOD/2) clk = ! clk;
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always #2500 test_data_in = test_data_in + 1;
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// 4 bit counting data, changing after some micro seconds
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always #3000 test_data_in = test_data_in + 1;
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// stimulus at upper gpio nibble
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assign gpio[7:4] = test_data_in;
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assign gpio[7:4] = test_data_in;
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// design under test instance
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picoblaze_wb_gpio dut (
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picoblaze_wb_gpio dut (
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.p_rst_i(rst),
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.p_rst_n_i(rst_n),
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.p_clk_i(clk),
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.p_clk_i(clk),
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.p_gpio_io(gpio)
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.p_gpio_io(gpio)
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);
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);
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