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[/] [wb4pb/] [trunk/] [sim/] [hdl/] [picoblaze_wb_gpio_tb.vhd] - Diff between revs 2 and 18
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Rev 18 |
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architecture behavioral of picoblaze_wb_gpio_tb is
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architecture behavioral of picoblaze_wb_gpio_tb is
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component picoblaze_wb_gpio is
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component picoblaze_wb_gpio is
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port
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port
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(
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(
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p_rst_i : in std_logic;
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p_rst_n_i : in std_logic;
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p_clk_i : in std_logic;
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p_clk_i : in std_logic;
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p_gpio_io : inout std_logic_vector(7 downto 0)
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p_gpio_io : inout std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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signal rst : std_logic := '1';
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signal rst_n : std_logic := '0';
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signal clk : std_logic := '1';
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signal clk : std_logic := '1';
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signal gpio : std_logic_vector(7 downto 0) := (others => 'Z');
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signal gpio : std_logic_vector(7 downto 0) := (others => 'Z');
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constant PERIOD : time := 20 ns;
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constant PERIOD : time := 20 ns;
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signal test_data_in : std_logic_vector(7 downto 4) := (others => '0');
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signal test_data_in : std_logic_vector(7 downto 4) := (others => '0');
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begin
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begin
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rst <= '0' after PERIOD*2;
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-- system signal generation
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rst_n <= '1' after PERIOD*2;
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clk <= not clk after PERIOD/2;
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clk <= not clk after PERIOD/2;
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process
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-- 4 bit counting data, changing after some micro seconds
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begin
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test_data_in <= std_logic_vector(unsigned(test_data_in) + 1) after 3000 ns;
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wait for 2500 ns;
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-- stimulus at upper gpio nibble
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test_data_in <= std_logic_vector(unsigned(test_data_in) + 1);
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end process;
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gpio(7 downto 4) <= test_data_in;
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gpio(7 downto 4) <= test_data_in;
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-- design under test instance
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dut : picoblaze_wb_gpio
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dut : picoblaze_wb_gpio
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port map
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port map
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(
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(
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p_rst_i => rst,
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p_rst_n_i => rst_n,
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p_clk_i => clk,
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p_clk_i => clk,
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p_gpio_io => gpio
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p_gpio_io => gpio
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);
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);
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