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----------------------------------------------------------------------------------
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-- Company: VISENGI S.L. (www.visengi.com)
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-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
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--
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-- Create Date: 23:44:13 22/August/2008
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-- Project Name: Triple Port WISHBONE SPRAM Wrapper
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-- Tool versions: Xilinx ISE 9.2i
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-- Description:
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--
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-- Description: This is a wrapper for an inferred single port RAM, that converts it
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-- into a Three-port RAM with one WISHBONE slave interface for each port.
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--
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--
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-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
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-- That is you may use it in ANY project (commercial or not) without paying a cent.
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-- You are only required to include in the copyrights/about section of accompanying
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-- software and manuals of use that your system contains a "3P WB SPRAM Wrapper
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-- (C) VISENGI S.L. under LGPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, we would like to know if you use this core in a project of yours, just an email will do.
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--
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-- Please take good note of the disclaimer section of the LPGL license, as we don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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ENTITY tb_wb_Np_ram_vhd IS
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END tb_wb_Np_ram_vhd;
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ARCHITECTURE behavior OF tb_wb_Np_ram_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT wb_Np_ram
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PORT(
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wb_clk_i : IN std_logic;
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wb_rst_i : IN std_logic;
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wb1_cyc_i : IN std_logic;
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wb1_stb_i : IN std_logic;
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wb1_we_i : IN std_logic;
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wb1_adr_i : IN std_logic_vector(7 downto 0);
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wb1_dat_i : IN std_logic_vector(31 downto 0);
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wb2_cyc_i : IN std_logic;
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wb2_stb_i : IN std_logic;
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wb2_we_i : IN std_logic;
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wb2_adr_i : IN std_logic_vector(7 downto 0);
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wb2_dat_i : IN std_logic_vector(31 downto 0);
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wb3_cyc_i : IN std_logic;
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wb3_stb_i : IN std_logic;
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wb3_we_i : IN std_logic;
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wb3_adr_i : IN std_logic_vector(7 downto 0);
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wb3_dat_i : IN std_logic_vector(31 downto 0);
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wb1_dat_o : OUT std_logic_vector(31 downto 0);
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wb1_ack_o : OUT std_logic;
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wb2_dat_o : OUT std_logic_vector(31 downto 0);
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wb2_ack_o : OUT std_logic;
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wb3_dat_o : OUT std_logic_vector(31 downto 0);
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wb3_ack_o : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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SIGNAL wb_clk_i : std_logic := '0';
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SIGNAL wb_rst_i : std_logic := '0';
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SIGNAL wb1_cyc_i : std_logic := '0';
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SIGNAL wb1_stb_i : std_logic := '0';
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SIGNAL wb1_we_i : std_logic := '0';
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SIGNAL wb2_cyc_i : std_logic := '0';
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SIGNAL wb2_stb_i : std_logic := '0';
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SIGNAL wb2_we_i : std_logic := '0';
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SIGNAL wb3_cyc_i : std_logic := '0';
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SIGNAL wb3_stb_i : std_logic := '0';
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SIGNAL wb3_we_i : std_logic := '0';
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SIGNAL wb1_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL wb1_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
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SIGNAL wb2_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL wb2_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
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SIGNAL wb3_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL wb3_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
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--Outputs
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SIGNAL wb1_dat_o : std_logic_vector(31 downto 0);
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SIGNAL wb1_ack_o : std_logic;
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SIGNAL wb2_dat_o : std_logic_vector(31 downto 0);
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SIGNAL wb2_ack_o : std_logic;
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SIGNAL wb3_dat_o : std_logic_vector(31 downto 0);
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SIGNAL wb3_ack_o : std_logic;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: wb_Np_ram PORT MAP(
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wb_clk_i => wb_clk_i,
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wb_rst_i => wb_rst_i,
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wb1_cyc_i => wb1_cyc_i,
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wb1_stb_i => wb1_stb_i,
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wb1_we_i => wb1_we_i,
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wb1_adr_i => wb1_adr_i,
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wb1_dat_i => wb1_dat_i,
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wb1_dat_o => wb1_dat_o,
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wb1_ack_o => wb1_ack_o,
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wb2_cyc_i => wb2_cyc_i,
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wb2_stb_i => wb2_stb_i,
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wb2_we_i => wb2_we_i,
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wb2_adr_i => wb2_adr_i,
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wb2_dat_i => wb2_dat_i,
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wb2_dat_o => wb2_dat_o,
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wb2_ack_o => wb2_ack_o,
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wb3_cyc_i => wb3_cyc_i,
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wb3_stb_i => wb3_stb_i,
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wb3_we_i => wb3_we_i,
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wb3_adr_i => wb3_adr_i,
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wb3_dat_i => wb3_dat_i,
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wb3_dat_o => wb3_dat_o,
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wb3_ack_o => wb3_ack_o
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);
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wb1_control : process (wb_rst_i, wb_clk_i)
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variable WaitACKWB : std_logic;
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variable data : std_logic_vector(31 downto 0);
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variable State : integer;
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begin
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if (wb_rst_i = '1') then
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wb1_dat_i <= (others => '0');
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wb1_adr_i <= (others => '0');
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wb1_we_i <= '0';
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wb1_stb_i <= '0';
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wb1_cyc_i <= '0';
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data := (others => '0');
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WaitACKWB := '0';
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State := 0;
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elsif (wb_clk_i = '1' and wb_clk_i'event) then
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if (WaitACKWB = '1') then
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if (wb1_ack_o = '1') then
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WaitACKWB := '0';
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wb1_we_i <= '0';
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wb1_stb_i <= '0';
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wb1_cyc_i <= '0';
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data := wb1_dat_o;
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end if;
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end if;
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if (WaitACKWB = '0') then
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case State is
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when 0 => --init
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wb1_adr_i <= X"00";
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wb1_dat_i <= x"00000001";
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wb1_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 1 =>
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wb1_adr_i <= X"01";
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wb1_dat_i <= x"00000002";
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wb1_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 2 =>
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wb1_adr_i <= X"02";
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wb1_dat_i <= x"00000003";
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wb1_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 3 =>
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State := State + 1;
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when 4 =>
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wb1_adr_i <= X"00";
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wb1_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 5 =>
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State := State + 1;
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when 6 =>
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State := State + 1;
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when 7 =>
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wb1_adr_i <= X"01";
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wb1_dat_i <= data;
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wb1_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 8 =>
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wb1_adr_i <= X"05";
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wb1_dat_i <= x"00500FA0";
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wb1_we_i <= '1';
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WaitACKWB := '1';
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State := 0;
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when 45 =>
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report "-----------> Testbench Finished OK!" severity FAILURE; --everything went fine, it's just to stop the simulation
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when others =>
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null;
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end case;
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if (WaitACKWB = '1') then
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wb1_stb_i <= '1';
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wb1_cyc_i <= '1';
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end if;
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end if;
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end if;
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end process wb1_control;
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wb2_control : process (wb_rst_i, wb_clk_i)
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variable WaitACKWB : std_logic;
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variable data : std_logic_vector(31 downto 0);
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variable State : integer;
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begin
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if (wb_rst_i = '1') then
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wb2_dat_i <= (others => '0');
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wb2_adr_i <= (others => '0');
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wb2_we_i <= '0';
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wb2_stb_i <= '0';
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wb2_cyc_i <= '0';
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data := (others => '0');
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WaitACKWB := '0';
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State := 0;
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elsif (wb_clk_i = '1' and wb_clk_i'event) then
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if (WaitACKWB = '1') then
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if (wb2_ack_o = '1') then
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WaitACKWB := '0';
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wb2_we_i <= '0';
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wb2_stb_i <= '0';
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wb2_cyc_i <= '0';
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data := wb2_dat_o;
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end if;
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end if;
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if (WaitACKWB = '0') then
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case State is
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when 0 => --init
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wb2_adr_i <= X"05";
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wb2_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 1 =>
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State := State + 1;
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when 2 =>
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State := State + 1;
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when 3 =>
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State := State + 1;
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when 4 =>
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wb2_adr_i <= X"04";
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wb2_dat_i <= x"00000002";
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wb2_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 5 =>
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State := State + 1;
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when 6 =>
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State := State + 1;
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when 7 =>
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State := State + 1;
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when 8 =>
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wb2_adr_i <= X"03";
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wb2_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 9 =>
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State := State + 1;
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when 10 =>
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wb2_adr_i <= X"02";
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wb2_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 11 =>
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State := State + 1;
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when 12 =>
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State := State + 1;
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when 13 =>
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State := State + 1;
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when 14 =>
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wb2_adr_i <= X"01";
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wb2_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 15 =>
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State := State + 1;
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when 16 =>
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State := State + 1;
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when 17 =>
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wb2_adr_i <= X"05";
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wb2_dat_i <= data;
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wb2_we_i <= '1';
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WaitACKWB := '1';
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State := 0;
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when others =>
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null;
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end case;
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if (WaitACKWB = '1') then
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wb2_stb_i <= '1';
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wb2_cyc_i <= '1';
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end if;
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end if;
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end if;
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end process wb2_control;
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wb3_control : process (wb_rst_i, wb_clk_i)
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variable WaitACKWB : std_logic;
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variable data : std_logic_vector(31 downto 0);
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variable State : integer;
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begin
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if (wb_rst_i = '1') then
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wb3_dat_i <= (others => '0');
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wb3_adr_i <= (others => '0');
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wb3_we_i <= '0';
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wb3_stb_i <= '0';
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wb3_cyc_i <= '0';
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data := (others => '0');
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WaitACKWB := '0';
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State := 0;
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elsif (wb_clk_i = '1' and wb_clk_i'event) then
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if (WaitACKWB = '1') then
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if (wb3_ack_o = '1') then
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WaitACKWB := '0';
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wb3_we_i <= '0';
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wb3_stb_i <= '0';
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wb3_cyc_i <= '0';
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data := wb3_dat_o;
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end if;
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end if;
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if (WaitACKWB = '0') then
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case State is
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when 0 =>
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State := State + 1;
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when 1 => --init
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wb3_adr_i <= X"05";
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wb3_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 2 =>
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wb3_adr_i <= X"02";
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wb3_dat_i <= x"00000002";
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wb3_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 3 =>
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State := State + 1;
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when 4 =>
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wb3_adr_i <= X"01";
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wb3_dat_i <= x"00000003";
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wb3_we_i <= '1';
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WaitACKWB := '1';
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State := State + 1;
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when 5 =>
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wb3_adr_i <= X"05";
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wb3_we_i <= '0';
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WaitACKWB := '1';
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State := State + 1;
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when 6 =>
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State := State + 1;
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when 7 =>
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State := State + 1;
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when 8 =>
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wb3_adr_i <= X"01";
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wb3_dat_i <= data;
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wb3_we_i <= '1';
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WaitACKWB := '1';
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State := 0;
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when others =>
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null;
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end case;
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if (WaitACKWB = '1') then
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wb3_stb_i <= '1';
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wb3_cyc_i <= '1';
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end if;
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end if;
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end if;
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end process wb3_control;
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wb_rst_i <= '1', '0' after 60 ns; --active high
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Clocking : process --50 MHz -> T = 20 ns
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begin
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wb_clk_i <= '1';
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wait for 10 ns;
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wb_clk_i <= '0';
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wait for 10 ns;
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end process;
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END;
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No newline at end of file
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No newline at end of file
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