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----------------------------------------------------------------------------------
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-- Company: VISENGI S.L. (www.visengi.com)
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-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
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--
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-- Create Date: 23:44:13 22/August/2008
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-- Project Name: Triple Port WISHBONE SPRAM Wrapper
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-- Tool versions: Xilinx ISE 9.2i
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-- Description:
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--
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-- Description: This is a wrapper for an inferred single port RAM, that converts it
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-- into a Three-port RAM with one WISHBONE slave interface for each port.
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--
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--
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-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
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-- That is you may use it in ANY project (commercial or not) without paying a cent.
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-- You are only required to include in the copyrights/about section of accompanying
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-- software and manuals of use that your system contains a "3P WB SPRAM Wrapper
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-- (C) VISENGI S.L. under LGPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, we would like to know if you use this core in a project of yours, just an email will do.
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--
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-- Please take good note of the disclaimer section of the LPGL license, as we don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity wb_Np_ram is
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generic (data_width : integer := 32;
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addr_width : integer := 8);
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port (
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic;
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wb1_cyc_i : in std_logic;
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wb1_stb_i : in std_logic;
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wb1_we_i : in std_logic;
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wb1_adr_i : in std_logic_vector(addr_width-1 downto 0);
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wb1_dat_i : in std_logic_vector(data_width-1 downto 0);
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wb1_dat_o : out std_logic_vector(data_width-1 downto 0);
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wb1_ack_o : out std_logic;
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wb2_cyc_i : in std_logic;
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wb2_stb_i : in std_logic;
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wb2_we_i : in std_logic;
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wb2_adr_i : in std_logic_vector(addr_width-1 downto 0);
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wb2_dat_i : in std_logic_vector(data_width-1 downto 0);
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wb2_dat_o : out std_logic_vector(data_width-1 downto 0);
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wb2_ack_o : out std_logic;
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wb3_cyc_i : in std_logic;
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wb3_stb_i : in std_logic;
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wb3_we_i : in std_logic;
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wb3_adr_i : in std_logic_vector(addr_width-1 downto 0);
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wb3_dat_i : in std_logic_vector(data_width-1 downto 0);
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wb3_dat_o : out std_logic_vector(data_width-1 downto 0);
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wb3_ack_o : out std_logic);
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end wb_Np_ram;
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architecture Behavioral of wb_Np_ram is
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component sp_ram is --uncomment to use an inferred spram
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generic (data_width : integer := 32;
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addr_width : integer := 8);
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--component sp_ram_core is --uncomment to use the coregen spram
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port (
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clka: IN std_logic;
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wea: IN std_logic_vector(0 downto 0);
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addra: IN std_logic_vector(addr_width-1 downto 0);
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dina: IN std_logic_vector(data_width-1 downto 0);
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douta: OUT std_logic_vector(data_width-1 downto 0));
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end component;
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signal we: std_logic_vector(0 downto 0);
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signal a : std_logic_vector(addr_width-1 downto 0);
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signal d,q : std_logic_vector(data_width-1 downto 0);
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begin
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u_sp_ram : sp_ram --uncomment to use an inferred spram
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generic map (data_width,addr_width)
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--u_sp_ram : sp_ram_core --uncomment to use the coregen spram
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port map (
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clka => wb_clk_i,
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wea => we,
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addra => a,
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dina => d,
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douta => q);
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wb1_dat_o <= q;
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wb2_dat_o <= q;
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wb3_dat_o <= q;
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WB_interconnect: process (wb_clk_i, wb_rst_i)
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variable ack1, ack2, ack3 : std_logic;
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variable lock : integer;
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variable State : integer;
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begin
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if (wb_rst_i = '1') then
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we(0) <= '0';
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a <= (others => '0');
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d <= (others => '0');
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ack1 := '0';
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wb1_ack_o <= '0';
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ack2 := '0';
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wb2_ack_o <= '0';
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ack3 := '0';
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wb3_ack_o <= '0';
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lock := 0;
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State := 0;
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elsif (wb_clk_i = '1' and wb_clk_i'event) then
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--defaults (unless overriden afterwards)
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we(0) <= '0';
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case State is
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when 0 => --priority for wb1
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--unlockers
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if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
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if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
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if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
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if (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
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ack2 := '0';
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ack3 := '0';
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lock := 1;
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if (wb1_stb_i = '1' and ack1 = '0') then --operation request
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we(0) <= wb1_we_i;
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a <= wb1_adr_i;
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d <= wb1_dat_i;
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if (wb1_we_i = '1') then
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ack1 := '1'; --ack now and stay in this state waiting for new ops
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State := 1;
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else
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State := 11; --wait one cycle for operation to end
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end if;
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else
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ack1 := '0'; --force one cycle wait between operations
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--or else the wb master could issue a write, then receive two acks (first legal ack and then
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--a spurious one due to being in the cycle where the master is still reading the first ack)
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--followed by a read and misinterpret the spurious ack as an ack for the read
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end if;
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elsif (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack3 := '0';
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lock := 2;
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if (wb2_stb_i = '1' and ack2 = '0') then --operation request
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we(0) <= wb2_we_i;
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a <= wb2_adr_i;
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d <= wb2_dat_i;
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if (wb2_we_i = '1') then
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ack2 := '1'; --ack now and stay in this state waiting for new ops
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State := 2;
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else
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State := 12; --wait one cycle for operation to end
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end if;
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else
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ack2 := '0'; --force one cycle wait between operations
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end if;
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elsif (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack2 := '0';
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lock := 3;
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if (wb3_stb_i = '1' and ack3 = '0') then --operation request
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we(0) <= wb3_we_i;
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a <= wb3_adr_i;
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d <= wb3_dat_i;
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if (wb3_we_i = '1') then
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ack3 := '1'; --ack now and stay in this state waiting for new ops
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State := 0;
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else
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State := 13; --wait one cycle for operation to end
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end if;
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else
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ack3 := '0'; --force one cycle wait between operations
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end if;
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end if;
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when 1 => --priority for wb2 (same code as previous State but changing the order of the if...elsifs)
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--unlockers
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if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
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if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
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if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
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if (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack3 := '0';
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lock := 2;
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if (wb2_stb_i = '1' and ack2 = '0') then --operation request
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we(0) <= wb2_we_i;
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a <= wb2_adr_i;
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d <= wb2_dat_i;
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if (wb2_we_i = '1') then
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ack2 := '1'; --ack now and stay in this state waiting for new ops
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State := 2;
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else
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State := 12; --wait one cycle for operation to end
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end if;
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else
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ack2 := '0'; --force one cycle wait between operations
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end if;
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elsif (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack2 := '0';
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lock := 3;
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if (wb3_stb_i = '1' and ack3 = '0') then --operation request
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we(0) <= wb3_we_i;
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a <= wb3_adr_i;
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d <= wb3_dat_i;
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if (wb3_we_i = '1') then
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ack3 := '1'; --ack now and stay in this state waiting for new ops
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State := 0;
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else
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State := 13; --wait one cycle for operation to end
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end if;
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else
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ack3 := '0'; --force one cycle wait between operations
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end if;
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elsif (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
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ack2 := '0';
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ack3 := '0';
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lock := 1;
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if (wb1_stb_i = '1' and ack1 = '0') then --operation request
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we(0) <= wb1_we_i;
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a <= wb1_adr_i;
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d <= wb1_dat_i;
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if (wb1_we_i = '1') then
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ack1 := '1'; --ack now and stay in this state waiting for new ops
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State := 1;
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else
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State := 11; --wait one cycle for operation to end
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end if;
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else
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ack1 := '0'; --force one cycle wait between operations
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end if;
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end if;
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when 2 => --priority for wb3 (same code as previous State but changing the order of the if...elsifs)
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--unlockers
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if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
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if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
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if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
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if (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack2 := '0';
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lock := 3;
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if (wb3_stb_i = '1' and ack3 = '0') then --operation request
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we(0) <= wb3_we_i;
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a <= wb3_adr_i;
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d <= wb3_dat_i;
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if (wb3_we_i = '1') then
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ack3 := '1'; --ack now and stay in this state waiting for new ops
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State := 0;
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else
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State := 13; --wait one cycle for operation to end
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end if;
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else
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ack3 := '0'; --force one cycle wait between operations
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end if;
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elsif (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
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ack2 := '0';
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ack3 := '0';
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lock := 1;
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if (wb1_stb_i = '1' and ack1 = '0') then --operation request
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we(0) <= wb1_we_i;
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a <= wb1_adr_i;
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d <= wb1_dat_i;
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if (wb1_we_i = '1') then
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ack1 := '1'; --ack now and stay in this state waiting for new ops
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State := 1;
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else
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State := 11; --wait one cycle for operation to end
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end if;
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else
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ack1 := '0'; --force one cycle wait between operations
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end if;
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elsif (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
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ack1 := '0';
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ack3 := '0';
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lock := 2;
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if (wb2_stb_i = '1' and ack2 = '0') then --operation request
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we(0) <= wb2_we_i;
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a <= wb2_adr_i;
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d <= wb2_dat_i;
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if (wb2_we_i = '1') then
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ack2 := '1'; --ack now and stay in this state waiting for new ops
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State := 2;
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else
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State := 12; --wait one cycle for operation to end
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end if;
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else
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ack2 := '0'; --force one cycle wait between operations
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end if;
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end if;
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when 11 =>
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ack1 := '1'; --ack operation
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ack2 := '0';
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ack3 := '0';
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State := 1;
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when 12 =>
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ack1 := '0';
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ack2 := '1'; --ack operation
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ack3 := '0';
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State := 2;
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when 13 =>
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ack1 := '0';
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ack2 := '0';
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ack3 := '1'; --ack operation
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State := 0;
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when others => --sanity
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ack1 := '0';
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ack2 := '0';
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ack3 := '0';
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State := 0;
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end case;
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wb1_ack_o <= (ack1 and wb1_stb_i and wb1_cyc_i); --to don't ack aborted operations
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wb2_ack_o <= (ack2 and wb2_stb_i and wb2_cyc_i); --to don't ack aborted operations
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wb3_ack_o <= (ack3 and wb3_stb_i and wb3_cyc_i); --to don't ack aborted operations
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end if;
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end process WB_interconnect;
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end Behavioral;
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