| Line 1... |
Line 1... |
-- Generated by PERL program wishbone.pl. Do not edit this file.
|
-- Generated by PERL program wishbone.pl. Do not edit this file.
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--
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--
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-- For defines see wishbone.defines
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-- For defines see wishbone.defines
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--
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--
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-- Generated Fri Apr 30 16:20:22 2004
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-- Generated Thu Jun 24 14:29:34 2004
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--
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--
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-- Wishbone masters:
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-- Wishbone masters:
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-- or32_i
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-- or32_i
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-- or32_d
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-- or32_d
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-- debug
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-- ethernetm
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--
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--
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-- Wishbone slaves:
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-- Wishbone slaves:
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-- uart
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-- uart
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-- baseadr 0x90000000 - size 0x00100000
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-- baseadr 0x90000000 - size 0x01000000
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-- sdram_ctrl1
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-- baseadr 0x00000000 - size 0x10000000
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-- sdram_ctrl2
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-- baseadr 0x10000000 - size 0x10000000
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-- bootRAM
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-- bootRAM
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-- baseadr 0x00000000 - size 0x00100000
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-- baseadr 0xf0000000 - size 0x10000000
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-- ethernets
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-- baseadr 0x92000000 - size 0x01000000
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-----------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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|
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package intercon_package is
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package intercon_package is
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| Line 49... |
Line 57... |
cti_o : std_logic_vector(2 downto 0);
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cti_o : std_logic_vector(2 downto 0);
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cyc_o : std_logic;
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cyc_o : std_logic;
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stb_o : std_logic;
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stb_o : std_logic;
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end record;
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end record;
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|
|
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type debug_wbm_i_type is record
|
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dat_i : std_logic_vector(31 downto 0);
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err_i : std_logic;
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rty_i : std_logic;
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ack_i : std_logic;
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end record;
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type debug_wbm_o_type is record
|
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dat_o : std_logic_vector(31 downto 0);
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we_o : std_logic;
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sel_o : std_logic_vector(3 downto 0);
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adr_o : std_logic_vector(31 downto 0);
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cyc_o : std_logic;
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stb_o : std_logic;
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end record;
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type ethernetm_wbm_i_type is record
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dat_i : std_logic_vector(31 downto 0);
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err_i : std_logic;
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ack_i : std_logic;
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end record;
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type ethernetm_wbm_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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we_o : std_logic;
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sel_o : std_logic_vector(3 downto 0);
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adr_o : std_logic_vector(31 downto 0);
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bte_o : std_logic_vector(1 downto 0);
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cti_o : std_logic_vector(2 downto 0);
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cyc_o : std_logic;
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stb_o : std_logic;
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end record;
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type uart_wbs_i_type is record
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type uart_wbs_i_type is record
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dat_i : std_logic_vector(31 downto 0);
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dat_i : std_logic_vector(31 downto 0);
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we_i : std_logic;
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we_i : std_logic;
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sel_i : std_logic_vector(3 downto 0);
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sel_i : std_logic_vector(3 downto 0);
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adr_i : std_logic_vector(4 downto 0);
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adr_i : std_logic_vector(4 downto 0);
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| Line 61... |
Line 100... |
end record;
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end record;
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type uart_wbs_o_type is record
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type uart_wbs_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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dat_o : std_logic_vector(31 downto 0);
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ack_o : std_logic;
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ack_o : std_logic;
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end record;
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end record;
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type bootRAM_wbs_i_type is record
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type sdram_ctrl1_wbs_i_type is record
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dat_i : std_logic_vector(31 downto 0);
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we_i : std_logic;
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sel_i : std_logic_vector(3 downto 0);
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adr_i : std_logic_vector(23 downto 2);
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cti_i : std_logic_vector(2 downto 0);
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cyc_i : std_logic;
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stb_i : std_logic;
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end record;
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type sdram_ctrl1_wbs_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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ack_o : std_logic;
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end record;
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type sdram_ctrl2_wbs_i_type is record
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dat_i : std_logic_vector(31 downto 0);
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dat_i : std_logic_vector(31 downto 0);
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we_i : std_logic;
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we_i : std_logic;
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sel_i : std_logic_vector(3 downto 0);
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sel_i : std_logic_vector(3 downto 0);
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adr_i : std_logic_vector(23 downto 2);
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cti_i : std_logic_vector(2 downto 0);
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cyc_i : std_logic;
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stb_i : std_logic;
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end record;
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type sdram_ctrl2_wbs_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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ack_o : std_logic;
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end record;
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type bootRAM_wbs_i_type is record
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sel_i : std_logic_vector(3 downto 0);
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adr_i : std_logic_vector(11 downto 2);
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adr_i : std_logic_vector(11 downto 2);
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cyc_i : std_logic;
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cyc_i : std_logic;
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stb_i : std_logic;
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stb_i : std_logic;
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end record;
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end record;
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type bootRAM_wbs_o_type is record
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type bootRAM_wbs_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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dat_o : std_logic_vector(31 downto 0);
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ack_o : std_logic;
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ack_o : std_logic;
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end record;
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end record;
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type ethernets_wbs_i_type is record
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dat_i : std_logic_vector(31 downto 0);
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we_i : std_logic;
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sel_i : std_logic_vector(3 downto 0);
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adr_i : std_logic_vector(11 downto 2);
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cyc_i : std_logic;
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stb_i : std_logic;
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end record;
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type ethernets_wbs_o_type is record
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dat_o : std_logic_vector(31 downto 0);
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err_o : std_logic;
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ack_o : std_logic;
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end record;
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function "and" (
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function "and" (
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l : std_logic_vector;
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l : std_logic_vector;
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r : std_logic)
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r : std_logic)
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return std_logic_vector;
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return std_logic_vector;
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| Line 174... |
Line 250... |
or32_i_wbm_i : out or32_i_wbm_i_type;
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or32_i_wbm_i : out or32_i_wbm_i_type;
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or32_i_wbm_o : in or32_i_wbm_o_type;
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or32_i_wbm_o : in or32_i_wbm_o_type;
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-- or32_d
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-- or32_d
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or32_d_wbm_i : out or32_d_wbm_i_type;
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or32_d_wbm_i : out or32_d_wbm_i_type;
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or32_d_wbm_o : in or32_d_wbm_o_type;
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or32_d_wbm_o : in or32_d_wbm_o_type;
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-- debug
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debug_wbm_i : out debug_wbm_i_type;
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debug_wbm_o : in debug_wbm_o_type;
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-- ethernetm
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ethernetm_wbm_i : out ethernetm_wbm_i_type;
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ethernetm_wbm_o : in ethernetm_wbm_o_type;
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-- wishbone slave port(s)
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-- wishbone slave port(s)
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-- uart
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-- uart
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uart_wbs_i : out uart_wbs_i_type;
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uart_wbs_i : out uart_wbs_i_type;
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uart_wbs_o : in uart_wbs_o_type;
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uart_wbs_o : in uart_wbs_o_type;
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-- sdram_ctrl1
|
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sdram_ctrl1_wbs_i : out sdram_ctrl1_wbs_i_type;
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sdram_ctrl1_wbs_o : in sdram_ctrl1_wbs_o_type;
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-- sdram_ctrl2
|
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sdram_ctrl2_wbs_i : out sdram_ctrl2_wbs_i_type;
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sdram_ctrl2_wbs_o : in sdram_ctrl2_wbs_o_type;
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-- bootRAM
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-- bootRAM
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bootRAM_wbs_i : out bootRAM_wbs_i_type;
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bootRAM_wbs_i : out bootRAM_wbs_i_type;
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bootRAM_wbs_o : in bootRAM_wbs_o_type;
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bootRAM_wbs_o : in bootRAM_wbs_o_type;
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-- ethernets
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ethernets_wbs_i : out ethernets_wbs_i_type;
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ethernets_wbs_o : in ethernets_wbs_o_type;
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-- clock and reset
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-- clock and reset
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic);
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reset : in std_logic);
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end intercon;
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end intercon;
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architecture rtl of intercon is
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architecture rtl of intercon is
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| Line 208... |
Line 299... |
signal or32_d_adr_o : std_logic_vector(31 downto 0);
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signal or32_d_adr_o : std_logic_vector(31 downto 0);
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signal or32_d_bte_o : std_logic_vector(1 downto 0);
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signal or32_d_bte_o : std_logic_vector(1 downto 0);
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signal or32_d_cti_o : std_logic_vector(2 downto 0);
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signal or32_d_cti_o : std_logic_vector(2 downto 0);
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signal or32_d_cyc_o : std_logic;
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signal or32_d_cyc_o : std_logic;
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signal or32_d_stb_o : std_logic;
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signal or32_d_stb_o : std_logic;
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signal debug_dat_i : std_logic_vector(31 downto 0);
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signal debug_ack_i : std_logic;
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signal debug_err_i : std_logic;
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signal debug_rty_i : std_logic;
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signal debug_dat_o : std_logic_vector(31 downto 0);
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signal debug_we_o : std_logic;
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signal debug_sel_o : std_logic_vector(3 downto 0);
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signal debug_adr_o : std_logic_vector(31 downto 0);
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signal debug_cyc_o : std_logic;
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signal debug_stb_o : std_logic;
|
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signal ethernetm_dat_i : std_logic_vector(31 downto 0);
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signal ethernetm_ack_i : std_logic;
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signal ethernetm_err_i : std_logic;
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signal ethernetm_dat_o : std_logic_vector(31 downto 0);
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signal ethernetm_we_o : std_logic;
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signal ethernetm_sel_o : std_logic_vector(3 downto 0);
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signal ethernetm_adr_o : std_logic_vector(31 downto 0);
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signal ethernetm_bte_o : std_logic_vector(1 downto 0);
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signal ethernetm_cti_o : std_logic_vector(2 downto 0);
|
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signal ethernetm_cyc_o : std_logic;
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signal ethernetm_stb_o : std_logic;
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signal uart_dat_o : std_logic_vector(31 downto 0);
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signal uart_dat_o : std_logic_vector(31 downto 0);
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signal uart_ack_o : std_logic;
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signal uart_ack_o : std_logic;
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signal uart_dat_i : std_logic_vector(31 downto 0);
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signal uart_dat_i : std_logic_vector(31 downto 0);
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signal uart_we_i : std_logic;
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signal uart_we_i : std_logic;
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signal uart_sel_i : std_logic_vector(3 downto 0);
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signal uart_sel_i : std_logic_vector(3 downto 0);
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signal uart_adr_i : std_logic_vector(4 downto 0);
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signal uart_adr_i : std_logic_vector(4 downto 0);
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signal uart_cyc_i : std_logic;
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signal uart_cyc_i : std_logic;
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signal uart_stb_i : std_logic;
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signal uart_stb_i : std_logic;
|
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signal sdram_ctrl1_dat_o : std_logic_vector(31 downto 0);
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signal sdram_ctrl1_ack_o : std_logic;
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signal sdram_ctrl1_dat_i : std_logic_vector(31 downto 0);
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signal sdram_ctrl1_we_i : std_logic;
|
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signal sdram_ctrl1_sel_i : std_logic_vector(3 downto 0);
|
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signal sdram_ctrl1_adr_i : std_logic_vector(23 downto 2);
|
|
signal sdram_ctrl1_cti_i : std_logic_vector(2 downto 0);
|
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signal sdram_ctrl1_cyc_i : std_logic;
|
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signal sdram_ctrl1_stb_i : std_logic;
|
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signal sdram_ctrl2_dat_o : std_logic_vector(31 downto 0);
|
|
signal sdram_ctrl2_ack_o : std_logic;
|
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signal sdram_ctrl2_dat_i : std_logic_vector(31 downto 0);
|
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signal sdram_ctrl2_we_i : std_logic;
|
|
signal sdram_ctrl2_sel_i : std_logic_vector(3 downto 0);
|
|
signal sdram_ctrl2_adr_i : std_logic_vector(23 downto 2);
|
|
signal sdram_ctrl2_cti_i : std_logic_vector(2 downto 0);
|
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signal sdram_ctrl2_cyc_i : std_logic;
|
|
signal sdram_ctrl2_stb_i : std_logic;
|
signal bootRAM_dat_o : std_logic_vector(31 downto 0);
|
signal bootRAM_dat_o : std_logic_vector(31 downto 0);
|
signal bootRAM_ack_o : std_logic;
|
signal bootRAM_ack_o : std_logic;
|
signal bootRAM_dat_i : std_logic_vector(31 downto 0);
|
|
signal bootRAM_we_i : std_logic;
|
|
signal bootRAM_sel_i : std_logic_vector(3 downto 0);
|
signal bootRAM_sel_i : std_logic_vector(3 downto 0);
|
signal bootRAM_adr_i : std_logic_vector(11 downto 2);
|
signal bootRAM_adr_i : std_logic_vector(11 downto 2);
|
signal bootRAM_cyc_i : std_logic;
|
signal bootRAM_cyc_i : std_logic;
|
signal bootRAM_stb_i : std_logic;
|
signal bootRAM_stb_i : std_logic;
|
|
signal ethernets_dat_o : std_logic_vector(31 downto 0);
|
|
signal ethernets_ack_o : std_logic;
|
|
signal ethernets_err_o : std_logic;
|
|
signal ethernets_dat_i : std_logic_vector(31 downto 0);
|
|
signal ethernets_we_i : std_logic;
|
|
signal ethernets_sel_i : std_logic_vector(3 downto 0);
|
|
signal ethernets_adr_i : std_logic_vector(11 downto 2);
|
|
signal ethernets_cyc_i : std_logic;
|
|
signal ethernets_stb_i : std_logic;
|
|
signal or32_i_sdram_ctrl1_ss : std_logic; -- slave select
|
|
signal or32_i_sdram_ctrl1_bg : std_logic; -- bus grant
|
|
signal or32_i_sdram_ctrl2_ss : std_logic; -- slave select
|
|
signal or32_i_sdram_ctrl2_bg : std_logic; -- bus grant
|
signal or32_i_bootRAM_ss : std_logic; -- slave select
|
signal or32_i_bootRAM_ss : std_logic; -- slave select
|
signal or32_i_bootRAM_bg : std_logic; -- bus grant
|
signal or32_i_bootRAM_bg : std_logic; -- bus grant
|
signal or32_d_uart_ss : std_logic; -- slave select
|
signal or32_d_uart_ss : std_logic; -- slave select
|
signal or32_d_uart_bg : std_logic; -- bus grant
|
signal or32_d_uart_bg : std_logic; -- bus grant
|
|
signal or32_d_sdram_ctrl1_ss : std_logic; -- slave select
|
|
signal or32_d_sdram_ctrl1_bg : std_logic; -- bus grant
|
|
signal or32_d_sdram_ctrl2_ss : std_logic; -- slave select
|
|
signal or32_d_sdram_ctrl2_bg : std_logic; -- bus grant
|
signal or32_d_bootRAM_ss : std_logic; -- slave select
|
signal or32_d_bootRAM_ss : std_logic; -- slave select
|
signal or32_d_bootRAM_bg : std_logic; -- bus grant
|
signal or32_d_bootRAM_bg : std_logic; -- bus grant
|
|
signal or32_d_ethernets_ss : std_logic; -- slave select
|
|
signal or32_d_ethernets_bg : std_logic; -- bus grant
|
|
signal debug_sdram_ctrl1_ss : std_logic; -- slave select
|
|
signal debug_sdram_ctrl1_bg : std_logic; -- bus grant
|
|
signal debug_sdram_ctrl2_ss : std_logic; -- slave select
|
|
signal debug_sdram_ctrl2_bg : std_logic; -- bus grant
|
|
signal debug_bootRAM_ss : std_logic; -- slave select
|
|
signal debug_bootRAM_bg : std_logic; -- bus grant
|
|
signal ethernetm_sdram_ctrl1_ss : std_logic; -- slave select
|
|
signal ethernetm_sdram_ctrl1_bg : std_logic; -- bus grant
|
|
signal ethernetm_sdram_ctrl2_ss : std_logic; -- slave select
|
|
signal ethernetm_sdram_ctrl2_bg : std_logic; -- bus grant
|
begin -- rtl
|
begin -- rtl
|
or32_d_uart_bg <= or32_d_uart_ss and or32_d_cyc_o;
|
or32_d_uart_bg <= or32_d_uart_ss and or32_d_cyc_o;
|
|
arbiter_sdram_ctrl1 : block
|
|
signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
|
|
signal or32_i_trafic_limit : std_logic;
|
|
signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
|
|
signal or32_d_trafic_limit : std_logic;
|
|
signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
|
|
signal debug_trafic_limit : std_logic;
|
|
signal ethernetm_bg, ethernetm_bg_1, ethernetm_bg_2, ethernetm_bg_q : std_logic;
|
|
signal ethernetm_trafic_limit : std_logic;
|
|
signal ce, idle, ack : std_logic;
|
|
begin
|
|
ack <= sdram_ctrl1_ack_o;
|
|
|
|
trafic_supervision_1 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 3,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => or32_i_sdram_ctrl1_bg,
|
|
ce => ce,
|
|
trafic_limit => or32_i_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_2 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => or32_d_sdram_ctrl1_bg,
|
|
ce => ce,
|
|
trafic_limit => or32_d_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_3 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => debug_sdram_ctrl1_bg,
|
|
ce => ce,
|
|
trafic_limit => debug_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_4 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => ethernetm_sdram_ctrl1_bg,
|
|
ce => ce,
|
|
trafic_limit => ethernetm_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
or32_i_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if or32_i_bg_q='0' then
|
|
or32_i_bg_q <= or32_i_bg;
|
|
elsif ack='1' and (or32_i_cti_o="000" or or32_i_cti_o="111") then
|
|
or32_i_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
or32_d_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if or32_d_bg_q='0' then
|
|
or32_d_bg_q <= or32_d_bg;
|
|
elsif ack='1' and (or32_d_cti_o="000" or or32_d_cti_o="111") then
|
|
or32_d_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
debug_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if debug_bg_q='0' then
|
|
debug_bg_q <= debug_bg;
|
|
elsif ack='1' then
|
|
debug_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
ethernetm_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if ethernetm_bg_q='0' then
|
|
ethernetm_bg_q <= ethernetm_bg;
|
|
elsif ack='1' and (ethernetm_cti_o="000" or ethernetm_cti_o="111") then
|
|
ethernetm_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' and ethernetm_bg_q='0' else '0';
|
|
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_sdram_ctrl1_ss='1' and or32_i_trafic_limit='0' else '0';
|
|
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl1_ss='1' and or32_d_trafic_limit='0' else '0';
|
|
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_sdram_ctrl1_ss='1' and debug_trafic_limit='0' else '0';
|
|
ethernetm_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl1_ss='1' and ethernetm_trafic_limit='0' else '0';
|
|
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0') and or32_i_cyc_o='1' and or32_i_sdram_ctrl1_ss='1' else '0';
|
|
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl1_ss='1' else '0';
|
|
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_sdram_ctrl1_ss='1' else '0';
|
|
ethernetm_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0' and debug_bg_2='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl1_ss='1' else '0';
|
|
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
|
|
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
|
|
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
|
|
ethernetm_bg <= ethernetm_bg_q or ethernetm_bg_1 or ethernetm_bg_2;
|
|
ce <= (or32_i_cyc_o and or32_i_sdram_ctrl1_ss) or (or32_d_cyc_o and or32_d_sdram_ctrl1_ss) or (debug_cyc_o and debug_sdram_ctrl1_ss) or (ethernetm_cyc_o and ethernetm_sdram_ctrl1_ss) when idle='1' else '0';
|
|
or32_i_sdram_ctrl1_bg <= or32_i_bg;
|
|
or32_d_sdram_ctrl1_bg <= or32_d_bg;
|
|
debug_sdram_ctrl1_bg <= debug_bg;
|
|
ethernetm_sdram_ctrl1_bg <= ethernetm_bg;
|
|
end block arbiter_sdram_ctrl1;
|
|
arbiter_sdram_ctrl2 : block
|
|
signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
|
|
signal or32_i_trafic_limit : std_logic;
|
|
signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
|
|
signal or32_d_trafic_limit : std_logic;
|
|
signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
|
|
signal debug_trafic_limit : std_logic;
|
|
signal ethernetm_bg, ethernetm_bg_1, ethernetm_bg_2, ethernetm_bg_q : std_logic;
|
|
signal ethernetm_trafic_limit : std_logic;
|
|
signal ce, idle, ack : std_logic;
|
|
begin
|
|
ack <= sdram_ctrl2_ack_o;
|
|
|
|
trafic_supervision_1 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => or32_i_sdram_ctrl2_bg,
|
|
ce => ce,
|
|
trafic_limit => or32_i_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_2 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 3,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => or32_d_sdram_ctrl2_bg,
|
|
ce => ce,
|
|
trafic_limit => or32_d_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_3 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => debug_sdram_ctrl2_bg,
|
|
ce => ce,
|
|
trafic_limit => debug_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
trafic_supervision_4 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 6)
|
|
port map(
|
|
bg => ethernetm_sdram_ctrl2_bg,
|
|
ce => ce,
|
|
trafic_limit => ethernetm_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
or32_i_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if or32_i_bg_q='0' then
|
|
or32_i_bg_q <= or32_i_bg;
|
|
elsif ack='1' and (or32_i_cti_o="000" or or32_i_cti_o="111") then
|
|
or32_i_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
or32_d_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if or32_d_bg_q='0' then
|
|
or32_d_bg_q <= or32_d_bg;
|
|
elsif ack='1' and (or32_d_cti_o="000" or or32_d_cti_o="111") then
|
|
or32_d_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
debug_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if debug_bg_q='0' then
|
|
debug_bg_q <= debug_bg;
|
|
elsif ack='1' then
|
|
debug_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
ethernetm_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if ethernetm_bg_q='0' then
|
|
ethernetm_bg_q <= ethernetm_bg;
|
|
elsif ack='1' and (ethernetm_cti_o="000" or ethernetm_cti_o="111") then
|
|
ethernetm_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' and ethernetm_bg_q='0' else '0';
|
|
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_sdram_ctrl2_ss='1' and or32_i_trafic_limit='0' else '0';
|
|
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl2_ss='1' and or32_d_trafic_limit='0' else '0';
|
|
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_sdram_ctrl2_ss='1' and debug_trafic_limit='0' else '0';
|
|
ethernetm_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl2_ss='1' and ethernetm_trafic_limit='0' else '0';
|
|
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0') and or32_i_cyc_o='1' and or32_i_sdram_ctrl2_ss='1' else '0';
|
|
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_sdram_ctrl2_ss='1' else '0';
|
|
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_sdram_ctrl2_ss='1' else '0';
|
|
ethernetm_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and ethernetm_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0' and debug_bg_2='0') and ethernetm_cyc_o='1' and ethernetm_sdram_ctrl2_ss='1' else '0';
|
|
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
|
|
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
|
|
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
|
|
ethernetm_bg <= ethernetm_bg_q or ethernetm_bg_1 or ethernetm_bg_2;
|
|
ce <= (or32_i_cyc_o and or32_i_sdram_ctrl2_ss) or (or32_d_cyc_o and or32_d_sdram_ctrl2_ss) or (debug_cyc_o and debug_sdram_ctrl2_ss) or (ethernetm_cyc_o and ethernetm_sdram_ctrl2_ss) when idle='1' else '0';
|
|
or32_i_sdram_ctrl2_bg <= or32_i_bg;
|
|
or32_d_sdram_ctrl2_bg <= or32_d_bg;
|
|
debug_sdram_ctrl2_bg <= debug_bg;
|
|
ethernetm_sdram_ctrl2_bg <= ethernetm_bg;
|
|
end block arbiter_sdram_ctrl2;
|
arbiter_bootRAM : block
|
arbiter_bootRAM : block
|
signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
|
signal or32_i_bg, or32_i_bg_1, or32_i_bg_2, or32_i_bg_q : std_logic;
|
signal or32_i_trafic_limit : std_logic;
|
signal or32_i_trafic_limit : std_logic;
|
signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
|
signal or32_d_bg, or32_d_bg_1, or32_d_bg_2, or32_d_bg_q : std_logic;
|
signal or32_d_trafic_limit : std_logic;
|
signal or32_d_trafic_limit : std_logic;
|
|
signal debug_bg, debug_bg_1, debug_bg_2, debug_bg_q : std_logic;
|
|
signal debug_trafic_limit : std_logic;
|
signal ce, idle, ack : std_logic;
|
signal ce, idle, ack : std_logic;
|
begin
|
begin
|
ack <= bootRAM_ack_o;
|
ack <= bootRAM_ack_o;
|
|
|
trafic_supervision_1 : entity work.trafic_supervision
|
trafic_supervision_1 : entity work.trafic_supervision
|
generic map(
|
generic map(
|
priority => 3,
|
priority => 1,
|
tot_priority => 4)
|
tot_priority => 3)
|
port map(
|
port map(
|
bg => or32_i_bootRAM_bg,
|
bg => or32_i_bootRAM_bg,
|
ce => ce,
|
ce => ce,
|
trafic_limit => or32_i_trafic_limit,
|
trafic_limit => or32_i_trafic_limit,
|
clk => clk,
|
clk => clk,
|
reset => reset);
|
reset => reset);
|
|
|
trafic_supervision_2 : entity work.trafic_supervision
|
trafic_supervision_2 : entity work.trafic_supervision
|
generic map(
|
generic map(
|
priority => 1,
|
priority => 1,
|
tot_priority => 4)
|
tot_priority => 3)
|
port map(
|
port map(
|
bg => or32_d_bootRAM_bg,
|
bg => or32_d_bootRAM_bg,
|
ce => ce,
|
ce => ce,
|
trafic_limit => or32_d_trafic_limit,
|
trafic_limit => or32_d_trafic_limit,
|
clk => clk,
|
clk => clk,
|
reset => reset);
|
reset => reset);
|
|
|
|
trafic_supervision_3 : entity work.trafic_supervision
|
|
generic map(
|
|
priority => 1,
|
|
tot_priority => 3)
|
|
port map(
|
|
bg => debug_bootRAM_bg,
|
|
ce => ce,
|
|
trafic_limit => debug_trafic_limit,
|
|
clk => clk,
|
|
reset => reset);
|
|
|
process(clk,reset)
|
process(clk,reset)
|
begin
|
begin
|
if reset='1' then
|
if reset='1' then
|
or32_i_bg_q <= '0';
|
or32_i_bg_q <= '0';
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
| Line 289... |
Line 715... |
or32_d_bg_q <= '0';
|
or32_d_bg_q <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' else '0';
|
process(clk,reset)
|
|
begin
|
|
if reset='1' then
|
|
debug_bg_q <= '0';
|
|
elsif clk'event and clk='1' then
|
|
if debug_bg_q='0' then
|
|
debug_bg_q <= debug_bg;
|
|
elsif ack='1' then
|
|
debug_bg_q <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
idle <= '1' when or32_i_bg_q='0' and or32_d_bg_q='0' and debug_bg_q='0' else '0';
|
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' and or32_i_trafic_limit='0' else '0';
|
or32_i_bg_1 <= '1' when idle='1' and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' and or32_i_trafic_limit='0' else '0';
|
or32_d_bg_1 <= '1' when idle='1' and or32_i_bg_1='0' and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' and or32_d_trafic_limit='0' else '0';
|
or32_d_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0') and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' and or32_d_trafic_limit='0' else '0';
|
or32_i_bg_2 <= '1' when idle='1' and or32_d_bg_1='0' and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' else '0';
|
debug_bg_1 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0') and debug_cyc_o='1' and debug_bootRAM_ss='1' and debug_trafic_limit='0' else '0';
|
or32_d_bg_2 <= '1' when idle='1' and or32_i_bg_2='0' and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' else '0';
|
or32_i_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0') and or32_i_cyc_o='1' and or32_i_bootRAM_ss='1' else '0';
|
|
or32_d_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and or32_i_bg_2='0') and or32_d_cyc_o='1' and or32_d_bootRAM_ss='1' else '0';
|
|
debug_bg_2 <= '1' when idle='1' and (or32_i_bg_1='0' and or32_d_bg_1='0' and debug_bg_1='0' and or32_i_bg_2='0' and or32_d_bg_2='0') and debug_cyc_o='1' and debug_bootRAM_ss='1' else '0';
|
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
|
or32_i_bg <= or32_i_bg_q or or32_i_bg_1 or or32_i_bg_2;
|
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
|
or32_d_bg <= or32_d_bg_q or or32_d_bg_1 or or32_d_bg_2;
|
ce <= (or32_i_cyc_o and or32_i_bootRAM_ss) or (or32_d_cyc_o and or32_d_bootRAM_ss) when idle='1' else '0';
|
debug_bg <= debug_bg_q or debug_bg_1 or debug_bg_2;
|
|
ce <= (or32_i_cyc_o and or32_i_bootRAM_ss) or (or32_d_cyc_o and or32_d_bootRAM_ss) or (debug_cyc_o and debug_bootRAM_ss) when idle='1' else '0';
|
or32_i_bootRAM_bg <= or32_i_bg;
|
or32_i_bootRAM_bg <= or32_i_bg;
|
or32_d_bootRAM_bg <= or32_d_bg;
|
or32_d_bootRAM_bg <= or32_d_bg;
|
|
debug_bootRAM_bg <= debug_bg;
|
end block arbiter_bootRAM;
|
end block arbiter_bootRAM;
|
|
or32_d_ethernets_bg <= or32_d_ethernets_ss and or32_d_cyc_o;
|
decoder:block
|
decoder:block
|
begin
|
begin
|
or32_i_bootRAM_ss <= '1' when or32_i_adr_o(31 downto 20)="000000000000" else
|
or32_i_sdram_ctrl1_ss <= '1' when or32_i_adr_o(31 downto 28)="0000" else
|
|
'0';
|
|
or32_i_sdram_ctrl2_ss <= '1' when or32_i_adr_o(31 downto 28)="0001" else
|
|
'0';
|
|
or32_i_bootRAM_ss <= '1' when or32_i_adr_o(31 downto 28)="1111" else
|
|
'0';
|
|
or32_d_uart_ss <= '1' when or32_d_adr_o(31 downto 24)="10010000" else
|
|
'0';
|
|
or32_d_sdram_ctrl1_ss <= '1' when or32_d_adr_o(31 downto 28)="0000" else
|
|
'0';
|
|
or32_d_sdram_ctrl2_ss <= '1' when or32_d_adr_o(31 downto 28)="0001" else
|
|
'0';
|
|
or32_d_bootRAM_ss <= '1' when or32_d_adr_o(31 downto 28)="1111" else
|
|
'0';
|
|
or32_d_ethernets_ss <= '1' when or32_d_adr_o(31 downto 24)="10010010" else
|
|
'0';
|
|
debug_sdram_ctrl1_ss <= '1' when debug_adr_o(31 downto 28)="0000" else
|
|
'0';
|
|
debug_sdram_ctrl2_ss <= '1' when debug_adr_o(31 downto 28)="0001" else
|
|
'0';
|
|
debug_bootRAM_ss <= '1' when debug_adr_o(31 downto 28)="1111" else
|
'0';
|
'0';
|
or32_d_uart_ss <= '1' when or32_d_adr_o(31 downto 20)="100100000000" else
|
ethernetm_sdram_ctrl1_ss <= '1' when ethernetm_adr_o(31 downto 28)="0000" else
|
'0';
|
'0';
|
or32_d_bootRAM_ss <= '1' when or32_d_adr_o(31 downto 20)="000000000000" else
|
ethernetm_sdram_ctrl2_ss <= '1' when ethernetm_adr_o(31 downto 28)="0001" else
|
'0';
|
'0';
|
uart_adr_i <= or32_d_adr_o(4 downto 0);
|
uart_adr_i <= or32_d_adr_o(4 downto 0);
|
bootRAM_adr_i <= (or32_i_adr_o(11 downto 2) and or32_i_bootRAM_bg) or (or32_d_adr_o(11 downto 2) and or32_d_bootRAM_bg);
|
sdram_ctrl1_adr_i <= (or32_i_adr_o(23 downto 2) and or32_i_sdram_ctrl1_bg) or (or32_d_adr_o(23 downto 2) and or32_d_sdram_ctrl1_bg) or (debug_adr_o(23 downto 2) and debug_sdram_ctrl1_bg) or (ethernetm_adr_o(23 downto 2) and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_adr_i <= (or32_i_adr_o(23 downto 2) and or32_i_sdram_ctrl2_bg) or (or32_d_adr_o(23 downto 2) and or32_d_sdram_ctrl2_bg) or (debug_adr_o(23 downto 2) and debug_sdram_ctrl2_bg) or (ethernetm_adr_o(23 downto 2) and ethernetm_sdram_ctrl2_bg);
|
|
bootRAM_adr_i <= (or32_i_adr_o(11 downto 2) and or32_i_bootRAM_bg) or (or32_d_adr_o(11 downto 2) and or32_d_bootRAM_bg) or (debug_adr_o(11 downto 2) and debug_bootRAM_bg);
|
|
ethernets_adr_i <= or32_d_adr_o(11 downto 2);
|
end block decoder;
|
end block decoder;
|
|
|
-- cyc_i(s)
|
-- cyc_i(s)
|
uart_cyc_i <= (or32_d_cyc_o and or32_d_uart_bg);
|
uart_cyc_i <= (or32_d_cyc_o and or32_d_uart_bg);
|
bootRAM_cyc_i <= (or32_i_cyc_o and or32_i_bootRAM_bg) or (or32_d_cyc_o and or32_d_bootRAM_bg);
|
sdram_ctrl1_cyc_i <= (or32_i_cyc_o and or32_i_sdram_ctrl1_bg) or (or32_d_cyc_o and or32_d_sdram_ctrl1_bg) or (debug_cyc_o and debug_sdram_ctrl1_bg) or (ethernetm_cyc_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_cyc_i <= (or32_i_cyc_o and or32_i_sdram_ctrl2_bg) or (or32_d_cyc_o and or32_d_sdram_ctrl2_bg) or (debug_cyc_o and debug_sdram_ctrl2_bg) or (ethernetm_cyc_o and ethernetm_sdram_ctrl2_bg);
|
|
bootRAM_cyc_i <= (or32_i_cyc_o and or32_i_bootRAM_bg) or (or32_d_cyc_o and or32_d_bootRAM_bg) or (debug_cyc_o and debug_bootRAM_bg);
|
|
ethernets_cyc_i <= (or32_d_cyc_o and or32_d_ethernets_bg);
|
-- stb_i(s)
|
-- stb_i(s)
|
uart_stb_i <= (or32_d_stb_o and or32_d_uart_bg);
|
uart_stb_i <= (or32_d_stb_o and or32_d_uart_bg);
|
bootRAM_stb_i <= (or32_i_stb_o and or32_i_bootRAM_bg) or (or32_d_stb_o and or32_d_bootRAM_bg);
|
sdram_ctrl1_stb_i <= (or32_i_stb_o and or32_i_sdram_ctrl1_bg) or (or32_d_stb_o and or32_d_sdram_ctrl1_bg) or (debug_stb_o and debug_sdram_ctrl1_bg) or (ethernetm_stb_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_stb_i <= (or32_i_stb_o and or32_i_sdram_ctrl2_bg) or (or32_d_stb_o and or32_d_sdram_ctrl2_bg) or (debug_stb_o and debug_sdram_ctrl2_bg) or (ethernetm_stb_o and ethernetm_sdram_ctrl2_bg);
|
|
bootRAM_stb_i <= (or32_i_stb_o and or32_i_bootRAM_bg) or (or32_d_stb_o and or32_d_bootRAM_bg) or (debug_stb_o and debug_bootRAM_bg);
|
|
ethernets_stb_i <= (or32_d_stb_o and or32_d_ethernets_bg);
|
-- we_i(s)
|
-- we_i(s)
|
uart_we_i <= (or32_d_we_o and or32_d_uart_bg);
|
uart_we_i <= (or32_d_we_o and or32_d_uart_bg);
|
bootRAM_we_i <= (or32_d_we_o and or32_d_bootRAM_bg);
|
sdram_ctrl1_we_i <= (or32_d_we_o and or32_d_sdram_ctrl1_bg) or (debug_we_o and debug_sdram_ctrl1_bg) or (ethernetm_we_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_we_i <= (or32_d_we_o and or32_d_sdram_ctrl2_bg) or (debug_we_o and debug_sdram_ctrl2_bg) or (ethernetm_we_o and ethernetm_sdram_ctrl2_bg);
|
|
ethernets_we_i <= (or32_d_we_o and or32_d_ethernets_bg);
|
-- ack_i(s)
|
-- ack_i(s)
|
or32_i_ack_i <= (bootRAM_ack_o and or32_i_bootRAM_bg);
|
or32_i_ack_i <= (sdram_ctrl1_ack_o and or32_i_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and or32_i_sdram_ctrl2_bg) or (bootRAM_ack_o and or32_i_bootRAM_bg);
|
or32_d_ack_i <= (uart_ack_o and or32_d_uart_bg) or (bootRAM_ack_o and or32_d_bootRAM_bg);
|
or32_d_ack_i <= (uart_ack_o and or32_d_uart_bg) or (sdram_ctrl1_ack_o and or32_d_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and or32_d_sdram_ctrl2_bg) or (bootRAM_ack_o and or32_d_bootRAM_bg) or (ethernets_ack_o and or32_d_ethernets_bg);
|
|
debug_ack_i <= (sdram_ctrl1_ack_o and debug_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and debug_sdram_ctrl2_bg) or (bootRAM_ack_o and debug_bootRAM_bg);
|
|
ethernetm_ack_i <= (sdram_ctrl1_ack_o and ethernetm_sdram_ctrl1_bg) or (sdram_ctrl2_ack_o and ethernetm_sdram_ctrl2_bg);
|
-- rty_i(s)
|
-- rty_i(s)
|
or32_i_rty_i <= '0';
|
or32_i_rty_i <= '0';
|
or32_d_rty_i <= '0';
|
or32_d_rty_i <= '0';
|
|
debug_rty_i <= '0';
|
-- err_i(s)
|
-- err_i(s)
|
or32_i_err_i <= '0';
|
or32_i_err_i <= '0';
|
or32_d_err_i <= '0';
|
or32_d_err_i <= '0';
|
|
debug_err_i <= '0';
|
|
ethernetm_err_i <= '0';
|
-- sel_i(s)
|
-- sel_i(s)
|
uart_sel_i <= (or32_d_sel_o and or32_d_uart_bg);
|
uart_sel_i <= (or32_d_sel_o and or32_d_uart_bg);
|
bootRAM_sel_i <= (or32_i_sel_o and or32_i_bootRAM_bg) or (or32_d_sel_o and or32_d_bootRAM_bg);
|
sdram_ctrl1_sel_i <= (or32_i_sel_o and or32_i_sdram_ctrl1_bg) or (or32_d_sel_o and or32_d_sdram_ctrl1_bg) or (debug_sel_o and debug_sdram_ctrl1_bg) or (ethernetm_sel_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_sel_i <= (or32_i_sel_o and or32_i_sdram_ctrl2_bg) or (or32_d_sel_o and or32_d_sdram_ctrl2_bg) or (debug_sel_o and debug_sdram_ctrl2_bg) or (ethernetm_sel_o and ethernetm_sdram_ctrl2_bg);
|
|
bootRAM_sel_i <= (or32_i_sel_o and or32_i_bootRAM_bg) or (or32_d_sel_o and or32_d_bootRAM_bg) or (debug_sel_o and debug_bootRAM_bg);
|
|
ethernets_sel_i <= (or32_d_sel_o and or32_d_ethernets_bg);
|
-- slave dat_i(s)
|
-- slave dat_i(s)
|
uart_dat_i <= or32_d_dat_o;
|
uart_dat_i <= or32_d_dat_o;
|
bootRAM_dat_i <= or32_d_dat_o;
|
sdram_ctrl1_dat_i <= (or32_d_dat_o and or32_d_sdram_ctrl1_bg) or (debug_dat_o and debug_sdram_ctrl1_bg) or (ethernetm_dat_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_dat_i <= (or32_d_dat_o and or32_d_sdram_ctrl2_bg) or (debug_dat_o and debug_sdram_ctrl2_bg) or (ethernetm_dat_o and ethernetm_sdram_ctrl2_bg);
|
|
ethernets_dat_i <= or32_d_dat_o;
|
-- master dat_i(s)
|
-- master dat_i(s)
|
or32_i_dat_i <= bootRAM_dat_o;
|
or32_i_dat_i <= (sdram_ctrl1_dat_o and or32_i_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and or32_i_sdram_ctrl2_bg) or (bootRAM_dat_o and or32_i_bootRAM_bg);
|
or32_d_dat_i <= (uart_dat_o and or32_d_uart_bg) or (bootRAM_dat_o and or32_d_bootRAM_bg);
|
or32_d_dat_i <= (uart_dat_o and or32_d_uart_bg) or (sdram_ctrl1_dat_o and or32_d_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and or32_d_sdram_ctrl2_bg) or (bootRAM_dat_o and or32_d_bootRAM_bg) or (ethernets_dat_o and or32_d_ethernets_bg);
|
|
debug_dat_i <= (sdram_ctrl1_dat_o and debug_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and debug_sdram_ctrl2_bg) or (bootRAM_dat_o and debug_bootRAM_bg);
|
|
ethernetm_dat_i <= (sdram_ctrl1_dat_o and ethernetm_sdram_ctrl1_bg) or (sdram_ctrl2_dat_o and ethernetm_sdram_ctrl2_bg);
|
-- tgc_i
|
-- tgc_i
|
|
sdram_ctrl1_cti_i <= (or32_i_cti_o and or32_i_sdram_ctrl1_bg) or (or32_d_cti_o and or32_d_sdram_ctrl1_bg) or (ethernetm_cti_o and ethernetm_sdram_ctrl1_bg);
|
|
sdram_ctrl2_cti_i <= (or32_i_cti_o and or32_i_sdram_ctrl2_bg) or (or32_d_cti_o and or32_d_sdram_ctrl2_bg) or (ethernetm_cti_o and ethernetm_sdram_ctrl2_bg);
|
-- tga_i
|
-- tga_i
|
or32_i_wbm_i.dat_i <= or32_i_dat_i;
|
or32_i_wbm_i.dat_i <= or32_i_dat_i;
|
or32_i_wbm_i.ack_i <= or32_i_ack_i ;
|
or32_i_wbm_i.ack_i <= or32_i_ack_i ;
|
or32_i_wbm_i.err_i <= or32_i_err_i;
|
or32_i_wbm_i.err_i <= or32_i_err_i;
|
or32_i_wbm_i.rty_i <= or32_i_rty_i;
|
or32_i_wbm_i.rty_i <= or32_i_rty_i;
|
| Line 363... |
Line 852... |
or32_d_adr_o <= or32_d_wbm_o.adr_o;
|
or32_d_adr_o <= or32_d_wbm_o.adr_o;
|
or32_d_cti_o <= or32_d_wbm_o.cti_o;
|
or32_d_cti_o <= or32_d_wbm_o.cti_o;
|
or32_d_bte_o <= or32_d_wbm_o.bte_o;
|
or32_d_bte_o <= or32_d_wbm_o.bte_o;
|
or32_d_cyc_o <= or32_d_wbm_o.cyc_o;
|
or32_d_cyc_o <= or32_d_wbm_o.cyc_o;
|
or32_d_stb_o <= or32_d_wbm_o.stb_o;
|
or32_d_stb_o <= or32_d_wbm_o.stb_o;
|
|
debug_wbm_i.dat_i <= debug_dat_i;
|
|
debug_wbm_i.ack_i <= debug_ack_i ;
|
|
debug_wbm_i.err_i <= debug_err_i;
|
|
debug_wbm_i.rty_i <= debug_rty_i;
|
|
debug_dat_o <= debug_wbm_o.dat_o;
|
|
debug_we_o <= debug_wbm_o.we_o;
|
|
debug_sel_o <= debug_wbm_o.sel_o;
|
|
debug_adr_o <= debug_wbm_o.adr_o;
|
|
debug_cyc_o <= debug_wbm_o.cyc_o;
|
|
debug_stb_o <= debug_wbm_o.stb_o;
|
|
ethernetm_wbm_i.dat_i <= ethernetm_dat_i;
|
|
ethernetm_wbm_i.ack_i <= ethernetm_ack_i ;
|
|
ethernetm_wbm_i.err_i <= ethernetm_err_i;
|
|
ethernetm_dat_o <= ethernetm_wbm_o.dat_o;
|
|
ethernetm_we_o <= ethernetm_wbm_o.we_o;
|
|
ethernetm_sel_o <= ethernetm_wbm_o.sel_o;
|
|
ethernetm_adr_o <= ethernetm_wbm_o.adr_o;
|
|
ethernetm_cti_o <= ethernetm_wbm_o.cti_o;
|
|
ethernetm_bte_o <= ethernetm_wbm_o.bte_o;
|
|
ethernetm_cyc_o <= ethernetm_wbm_o.cyc_o;
|
|
ethernetm_stb_o <= ethernetm_wbm_o.stb_o;
|
uart_dat_o <= uart_wbs_o.dat_o;
|
uart_dat_o <= uart_wbs_o.dat_o;
|
uart_ack_o <= uart_wbs_o.ack_o;
|
uart_ack_o <= uart_wbs_o.ack_o;
|
uart_wbs_i.dat_i <= uart_dat_i;
|
uart_wbs_i.dat_i <= uart_dat_i;
|
uart_wbs_i.we_i <= uart_we_i;
|
uart_wbs_i.we_i <= uart_we_i;
|
uart_wbs_i.sel_i <= uart_sel_i;
|
uart_wbs_i.sel_i <= uart_sel_i;
|
uart_wbs_i.adr_i <= uart_adr_i;
|
uart_wbs_i.adr_i <= uart_adr_i;
|
uart_wbs_i.cyc_i <= uart_cyc_i;
|
uart_wbs_i.cyc_i <= uart_cyc_i;
|
uart_wbs_i.stb_i <= uart_stb_i;
|
uart_wbs_i.stb_i <= uart_stb_i;
|
|
sdram_ctrl1_dat_o <= sdram_ctrl1_wbs_o.dat_o;
|
|
sdram_ctrl1_ack_o <= sdram_ctrl1_wbs_o.ack_o;
|
|
sdram_ctrl1_wbs_i.dat_i <= sdram_ctrl1_dat_i;
|
|
sdram_ctrl1_wbs_i.we_i <= sdram_ctrl1_we_i;
|
|
sdram_ctrl1_wbs_i.sel_i <= sdram_ctrl1_sel_i;
|
|
sdram_ctrl1_wbs_i.adr_i <= sdram_ctrl1_adr_i;
|
|
sdram_ctrl1_wbs_i.cti_i <= sdram_ctrl1_cti_i;
|
|
sdram_ctrl1_wbs_i.cyc_i <= sdram_ctrl1_cyc_i;
|
|
sdram_ctrl1_wbs_i.stb_i <= sdram_ctrl1_stb_i;
|
|
sdram_ctrl2_dat_o <= sdram_ctrl2_wbs_o.dat_o;
|
|
sdram_ctrl2_ack_o <= sdram_ctrl2_wbs_o.ack_o;
|
|
sdram_ctrl2_wbs_i.dat_i <= sdram_ctrl2_dat_i;
|
|
sdram_ctrl2_wbs_i.we_i <= sdram_ctrl2_we_i;
|
|
sdram_ctrl2_wbs_i.sel_i <= sdram_ctrl2_sel_i;
|
|
sdram_ctrl2_wbs_i.adr_i <= sdram_ctrl2_adr_i;
|
|
sdram_ctrl2_wbs_i.cti_i <= sdram_ctrl2_cti_i;
|
|
sdram_ctrl2_wbs_i.cyc_i <= sdram_ctrl2_cyc_i;
|
|
sdram_ctrl2_wbs_i.stb_i <= sdram_ctrl2_stb_i;
|
bootRAM_dat_o <= bootRAM_wbs_o.dat_o;
|
bootRAM_dat_o <= bootRAM_wbs_o.dat_o;
|
bootRAM_ack_o <= bootRAM_wbs_o.ack_o;
|
bootRAM_ack_o <= bootRAM_wbs_o.ack_o;
|
bootRAM_wbs_i.dat_i <= bootRAM_dat_i;
|
|
bootRAM_wbs_i.we_i <= bootRAM_we_i;
|
|
bootRAM_wbs_i.sel_i <= bootRAM_sel_i;
|
bootRAM_wbs_i.sel_i <= bootRAM_sel_i;
|
bootRAM_wbs_i.adr_i <= bootRAM_adr_i;
|
bootRAM_wbs_i.adr_i <= bootRAM_adr_i;
|
bootRAM_wbs_i.cyc_i <= bootRAM_cyc_i;
|
bootRAM_wbs_i.cyc_i <= bootRAM_cyc_i;
|
bootRAM_wbs_i.stb_i <= bootRAM_stb_i;
|
bootRAM_wbs_i.stb_i <= bootRAM_stb_i;
|
|
ethernets_dat_o <= ethernets_wbs_o.dat_o;
|
|
ethernets_ack_o <= ethernets_wbs_o.ack_o;
|
|
ethernets_err_o <= ethernets_wbs_o.err_o;
|
|
ethernets_wbs_i.dat_i <= ethernets_dat_i;
|
|
ethernets_wbs_i.we_i <= ethernets_we_i;
|
|
ethernets_wbs_i.sel_i <= ethernets_sel_i;
|
|
ethernets_wbs_i.adr_i <= ethernets_adr_i;
|
|
ethernets_wbs_i.cyc_i <= ethernets_cyc_i;
|
|
ethernets_wbs_i.stb_i <= ethernets_stb_i;
|
end rtl;
|
end rtl;
|
No newline at end of file
|
No newline at end of file
|
