OpenCores

Rev 9	Rev 12
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $`	`// $Id: test_bench_top.v,v 1.4 2001-10-19 04:47:31 rudi Exp $`
`//`	`//`
`// $Date: 2001-09-07 15:34:36 $`	`// $Date: 2001-10-19 04:47:31 $`
`// $Revision: 1.3 $`	`// $Revision: 1.4 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2001/09/07 15:34:36 rudi`
	`//`
	`// Changed reset to active high.`
	`//`
`// Revision 1.2 2001/08/15 05:40:29 rudi`	`// Revision 1.2 2001/08/15 05:40:29 rudi`
`//`	`//`
`// - Changed IO names to be more clear.`	`// - Changed IO names to be more clear.`
`// - Uniquifyed define names to be core specific.`	`// - Uniquifyed define names to be core specific.`
`// - Added Section 3.10, describing DMA restart.`	`// - Added Section 3.10, describing DMA restart.`
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`//`	`//`
`//`	`//`

`include "wb_dma_defines.v"	`include "wb_dma_defines.v"

	`define CH_COUNT 4

`module test;`	`module test;`

`reg clk;`	`reg clk;`
`reg rst;`	`reg rst;`

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`wire wb1_cyc_o;`	`wire wb1_cyc_o;`
`wire wb1_stb_o;`	`wire wb1_stb_o;`
`wire wb1_ack_i;`	`wire wb1_ack_i;`
`wire wb1_err_i;`	`wire wb1_err_i;`
`wire wb1_rty_i;`	`wire wb1_rty_i;`
reg [`WDMA_CH_COUNT-1:0] req_i;	reg [`CH_COUNT-1:0] req_i;
wire [`WDMA_CH_COUNT-1:0] ack_o;	wire [`CH_COUNT-1:0] ack_o;
reg [`WDMA_CH_COUNT-1:0] nd_i;	reg [`CH_COUNT-1:0] nd_i;
reg [`WDMA_CH_COUNT-1:0] rest_i;	reg [`CH_COUNT-1:0] rest_i;
`wire inta_o;`	`wire inta_o;`
`wire intb_o;`	`wire intb_o;`

`wire [31:0] wb0_data_o_mast;`	`wire [31:0] wb0_data_o_mast;`
`wire [31:0] wb1_data_o_mast;`	`wire [31:0] wb1_data_o_mast;`
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`//`	`//`


`// Module Prototype`	`// Module Prototype`

`wb_dma_top u0(`	`wb_dma_top`
	`#( 4'hb, // register file address`
	`2'd1, // Number of priorities (4)`
	`CH_COUNT, // Number of channels
	`4'hf,`
	`4'hf,`
	`4'hf,`
	`4'hf,`
	`4'hf,`
	`4'hf,`
	`4'hf,`
	`4'hf`
	`)`

	`u0(`
`.clk_i( clk ),`	`.clk_i( clk ),`
`.rst_i( rst ),`	`.rst_i( rst ),`
`.wb0s_data_i( wb0s_data_i ),`	`.wb0s_data_i( wb0s_data_i ),`
`.wb0s_data_o( wb0s_data_o ),`	`.wb0s_data_o( wb0s_data_o ),`
`.wb0_addr_i( wb0_addr_i ),`	`.wb0_addr_i( wb0_addr_i ),`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $

//  $Id: test_bench_top.v,v 1.4 2001-10-19 04:47:31 rudi Exp $

//

//

//  $Date: 2001-09-07 15:34:36 $

//  $Date: 2001-10-19 04:47:31 $

//  $Revision: 1.3 $

//  $Revision: 1.4 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.3  2001/09/07 15:34:36  rudi

//

//               Changed reset to active high.

//

//               Revision 1.2  2001/08/15 05:40:29  rudi

//               Revision 1.2  2001/08/15 05:40:29  rudi

//

//

//               - Changed IO names to be more clear.

//               - Changed IO names to be more clear.

//               - Uniquifyed define names to be core specific.

//               - Uniquifyed define names to be core specific.

//               - Added Section 3.10, describing DMA restart.

//               - Added Section 3.10, describing DMA restart.

Line 65...

Line 69...

//

//

//

//

`include "wb_dma_defines.v"

`include "wb_dma_defines.v"

`define CH_COUNT 4

module test;

module test;

reg             clk;

reg             clk;

reg             rst;

reg             rst;

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Line 118...

wire            wb1_cyc_o;

wire            wb1_cyc_o;

wire            wb1_stb_o;

wire            wb1_stb_o;

wire            wb1_ack_i;

wire            wb1_ack_i;

wire            wb1_err_i;

wire            wb1_err_i;

wire            wb1_rty_i;

wire            wb1_rty_i;

reg     [`WDMA_CH_COUNT-1:0]     req_i;

reg     [`CH_COUNT-1:0]  req_i;

wire    [`WDMA_CH_COUNT-1:0]     ack_o;

wire    [`CH_COUNT-1:0]  ack_o;

reg     [`WDMA_CH_COUNT-1:0]     nd_i;

reg     [`CH_COUNT-1:0]  nd_i;

reg     [`WDMA_CH_COUNT-1:0]     rest_i;

reg     [`CH_COUNT-1:0]  rest_i;

wire            inta_o;

wire            inta_o;

wire            intb_o;

wire            intb_o;

wire    [31:0]   wb0_data_o_mast;

wire    [31:0]   wb0_data_o_mast;

wire    [31:0]   wb1_data_o_mast;

wire    [31:0]   wb1_data_o_mast;

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Line 314...

//

//

// Module Prototype

// Module Prototype

wb_dma_top      u0(

wb_dma_top

        #(      4'hb,           // register file address

                2'd1,           // Number of priorities (4)

                `CH_COUNT,      // Number of channels

                4'hf,

                4'hf,

                4'hf,

                4'hf,

                4'hf,

                4'hf,

                4'hf,

                4'hf

u0(

                .clk_i(         clk             ),

                .clk_i(         clk             ),

                .rst_i(         rst             ),

                .rst_i(         rst             ),

                .wb0s_data_i(   wb0s_data_i     ),

                .wb0s_data_i(   wb0s_data_i     ),

                .wb0s_data_o(   wb0s_data_o     ),

                .wb0s_data_o(   wb0s_data_o     ),

                .wb0_addr_i(    wb0_addr_i      ),

                .wb0_addr_i(    wb0_addr_i      ),

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[/] [wb_dma/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 9 and 12