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[/] [wb_dma/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 8 and 9

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Rev 8 Rev 9
Line 35... Line 35...
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: test_bench_top.v,v 1.2 2001-08-15 05:40:29 rudi Exp $
//  $Id: test_bench_top.v,v 1.3 2001-09-07 15:34:36 rudi Exp $
//
//
//  $Date: 2001-08-15 05:40:29 $
//  $Date: 2001-09-07 15:34:36 $
//  $Revision: 1.2 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Author: rudi $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.2  2001/08/15 05:40:29  rudi
 
//
 
//               - Changed IO names to be more clear.
 
//               - Uniquifyed define names to be core specific.
 
//               - Added Section 3.10, describing DMA restart.
 
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//
//
//               1) Changed Directory Structure
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//               2) Added restart signal (REST)
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// Defines 
// Defines 
//
//
 
 
 
 
`define MEM             32'h0002_0000
`define MEM             32'h0002_0000
`define REG_BASE        32'hff00_0000
`define REG_BASE        32'hb000_0000
 
 
`define COR             8'h0
`define COR             8'h0
`define INT_MASKA       8'h4
`define INT_MASKA       8'h4
`define INT_MASKB       8'h8
`define INT_MASKB       8'h8
`define INT_SRCA        8'hc
`define INT_SRCA        8'hc
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        wd_cnt = 0;
        wd_cnt = 0;
        ack_cnt = 0;
        ack_cnt = 0;
        ack_cnt_clr = 0;
        ack_cnt_clr = 0;
        error_cnt = 0;
        error_cnt = 0;
        clk = 0;
        clk = 0;
        rst = 0;
        rst = 1;
        rest_i = 0;
        rest_i = 0;
 
 
        repeat(10)      @(posedge clk);
        repeat(10)      @(posedge clk);
        rst = 1;
        rst = 0;
        repeat(10)      @(posedge clk);
        repeat(10)      @(posedge clk);
 
 
        // HERE IS WHERE THE TEST CASES GO ...
        // HERE IS WHERE THE TEST CASES GO ...
 
 
if(1)   // Full Regression Run
if(0)    // Full Regression Run
   begin
   begin
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :    Long Regression Run ...                         :");
 
$display(" :....................................................:");
        pt10_rd;
        pt10_rd;
        pt01_wr;
        pt01_wr;
        pt01_rd;
        pt01_rd;
        pt10_wr;
        pt10_wr;
        sw_dma1(0);
        sw_dma1(0);
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        hw_dma4(0);
        hw_dma4(0);
   end
   end
else
else
if(1)   // Quick Regression Run
if(1)   // Quick Regression Run
   begin
   begin
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :    Short Regression Run ...                        :");
 
$display(" :....................................................:");
        pt10_rd;
        pt10_rd;
        pt01_wr;
        pt01_wr;
        pt01_rd;
        pt01_rd;
        pt10_wr;
        pt10_wr;
        sw_dma1(2);
        sw_dma1(2);
Line 243... Line 257...
   begin
   begin
 
 
        //
        //
        // TEST DEVELOPMENT AREA
        // TEST DEVELOPMENT AREA
        //
        //
 
        sw_dma1(3);
 
 
        arb_test1;
        //arb_test1;
 
 
        repeat(100)     @(posedge clk);
        repeat(100)     @(posedge clk);
 
 
   end
   end
 
 
Line 346... Line 361...
                .intb_o(        intb_o          )
                .intb_o(        intb_o          )
                );
                );
 
 
wb_slv  #(14) s0(
wb_slv  #(14) s0(
                .clk(           clk             ),
                .clk(           clk             ),
                .rst(           rst             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_o      ),
                .adr(           wb0_addr_o      ),
                .din(           wb0s_data_o     ),
                .din(           wb0s_data_o     ),
                .dout(          wb0s_data_i     ),
                .dout(          wb0s_data_i     ),
                .cyc(           wb0_cyc_o       ),
                .cyc(           wb0_cyc_o       ),
                .stb(           wb0_stb_o       ),
                .stb(           wb0_stb_o       ),
Line 361... Line 376...
                .rty(           wb0_rty_i       )
                .rty(           wb0_rty_i       )
                );
                );
 
 
wb_slv  #(14) s1(
wb_slv  #(14) s1(
                .clk(           clk             ),
                .clk(           clk             ),
                .rst(           rst             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_o      ),
                .adr(           wb1_addr_o      ),
                .din(           wb1s_data_o     ),
                .din(           wb1s_data_o     ),
                .dout(          wb1s_data_i     ),
                .dout(          wb1s_data_i     ),
                .cyc(           wb1_cyc_o       ),
                .cyc(           wb1_cyc_o       ),
                .stb(           wb1_stb_o       ),
                .stb(           wb1_stb_o       ),
Line 376... Line 391...
                .rty(           wb1_rty_i       )
                .rty(           wb1_rty_i       )
                );
                );
 
 
wb_mast m0(
wb_mast m0(
                .clk(           clk             ),
                .clk(           clk             ),
                .rst(           rst             ),
                .rst(           ~rst            ),
                .adr(           wb0_addr_i      ),
                .adr(           wb0_addr_i      ),
                .din(           wb0m_data_o     ),
                .din(           wb0m_data_o     ),
                .dout(          wb0m_data_i     ),
                .dout(          wb0m_data_i     ),
                .cyc(           wb0_cyc_i       ),
                .cyc(           wb0_cyc_i       ),
                .stb(           wb0_stb_i       ),
                .stb(           wb0_stb_i       ),
Line 391... Line 406...
                .rty(           wb0_rty_o       )
                .rty(           wb0_rty_o       )
                );
                );
 
 
wb_mast m1(
wb_mast m1(
                .clk(           clk             ),
                .clk(           clk             ),
                .rst(           rst             ),
                .rst(           ~rst            ),
                .adr(           wb1_addr_i      ),
                .adr(           wb1_addr_i      ),
                .din(           wb1m_data_o     ),
                .din(           wb1m_data_o     ),
                .dout(          wb1m_data_i     ),
                .dout(          wb1m_data_i     ),
                .cyc(           wb1_cyc_i       ),
                .cyc(           wb1_cyc_i       ),
                .stb(           wb1_stb_i       ),
                .stb(           wb1_stb_i       ),

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