OpenCores

Rev 6	Rev 8
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`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: wb_dma_ch_pri_enc.v,v 1.2 2001-08-07 08:00:43 rudi Exp $`	`// $Id: wb_dma_ch_pri_enc.v,v 1.3 2001-08-15 05:40:30 rudi Exp $`
`//`	`//`
`// $Date: 2001-08-07 08:00:43 $`	`// $Date: 2001-08-15 05:40:30 $`
`// $Revision: 1.2 $`	`// $Revision: 1.3 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2001/08/07 08:00:43 rudi`
	`//`
	`//`
	`// Split up priority encoder modules to separate files`
	`//`
`// Revision 1.1 2001/07/29 08:57:02 rudi`	`// Revision 1.1 2001/07/29 08:57:02 rudi`
`//`	`//`
`//`	`//`
`// 1) Changed Directory Structure`	`// 1) Changed Directory Structure`
`// 2) Added restart signal (REST)`	`// 2) Added restart signal (REST)`
Line 108...	Line 113...
`wire [7:0] pri28_out, pri29_out, pri30_out;`	`wire [7:0] pri28_out, pri29_out, pri30_out;`

`wire [7:0] pri_out_tmp;`	`wire [7:0] pri_out_tmp;`
`reg [2:0] pri_out;`	`reg [2:0] pri_out;`

`ifdef HAVE_CH1	`ifdef WDMA_HAVE_CH1
`wb_dma_pri_enc_sub u0(`	`wb_dma_pri_enc_sub u0(`
`.valid( valid[0] ),`	`.valid( valid[0] ),`
`.pri_in( pri0 ),`	`.pri_in( pri0 ),`
`.pri_out( pri0_out )`	`.pri_out( pri0_out )`
`);`	`);`
Line 125...	Line 130...
`else	`else
`assign pri0_out = 0;`	`assign pri0_out = 0;`
`assign pri1_out = 0;`	`assign pri1_out = 0;`
`endif	`endif

`ifdef HAVE_CH2	`ifdef WDMA_HAVE_CH2
`wb_dma_pri_enc_sub u2(`	`wb_dma_pri_enc_sub u2(`
`.valid( valid[2] ),`	`.valid( valid[2] ),`
`.pri_in( pri2 ),`	`.pri_in( pri2 ),`
`.pri_out( pri2_out )`	`.pri_out( pri2_out )`
`);`	`);`
`else	`else
`assign pri2_out = 0;`	`assign pri2_out = 0;`
`endif	`endif

`ifdef HAVE_CH3	`ifdef WDMA_HAVE_CH3
`wb_dma_pri_enc_sub u3(`	`wb_dma_pri_enc_sub u3(`
`.valid( valid[3] ),`	`.valid( valid[3] ),`
`.pri_in( pri3 ),`	`.pri_in( pri3 ),`
`.pri_out( pri3_out )`	`.pri_out( pri3_out )`
`);`	`);`
`else	`else
`assign pri3_out = 0;`	`assign pri3_out = 0;`
`endif	`endif

`ifdef HAVE_CH4	`ifdef WDMA_HAVE_CH4
`wb_dma_pri_enc_sub u4(`	`wb_dma_pri_enc_sub u4(`
`.valid( valid[4] ),`	`.valid( valid[4] ),`
`.pri_in( pri4 ),`	`.pri_in( pri4 ),`
`.pri_out( pri4_out )`	`.pri_out( pri4_out )`
`);`	`);`
`else	`else
`assign pri4_out = 0;`	`assign pri4_out = 0;`
`endif	`endif

`ifdef HAVE_CH5	`ifdef WDMA_HAVE_CH5
`wb_dma_pri_enc_sub u5(`	`wb_dma_pri_enc_sub u5(`
`.valid( valid[5] ),`	`.valid( valid[5] ),`
`.pri_in( pri5 ),`	`.pri_in( pri5 ),`
`.pri_out( pri5_out )`	`.pri_out( pri5_out )`
`);`	`);`
`else	`else
`assign pri5_out = 0;`	`assign pri5_out = 0;`
`endif	`endif

`ifdef HAVE_CH6	`ifdef WDMA_HAVE_CH6
`wb_dma_pri_enc_sub u6(`	`wb_dma_pri_enc_sub u6(`
`.valid( valid[6] ),`	`.valid( valid[6] ),`
`.pri_in( pri6 ),`	`.pri_in( pri6 ),`
`.pri_out( pri6_out )`	`.pri_out( pri6_out )`
`);`	`);`
`else	`else
`assign pri6_out = 0;`	`assign pri6_out = 0;`
`endif	`endif

`ifdef HAVE_CH7	`ifdef WDMA_HAVE_CH7
`wb_dma_pri_enc_sub u7(`	`wb_dma_pri_enc_sub u7(`
`.valid( valid[7] ),`	`.valid( valid[7] ),`
`.pri_in( pri7 ),`	`.pri_in( pri7 ),`
`.pri_out( pri7_out )`	`.pri_out( pri7_out )`
`);`	`);`
`else	`else
`assign pri7_out = 0;`	`assign pri7_out = 0;`
`endif	`endif

`ifdef HAVE_CH8	`ifdef WDMA_HAVE_CH8
`wb_dma_pri_enc_sub u8(`	`wb_dma_pri_enc_sub u8(`
`.valid( valid[8] ),`	`.valid( valid[8] ),`
`.pri_in( pri8 ),`	`.pri_in( pri8 ),`
`.pri_out( pri8_out )`	`.pri_out( pri8_out )`
`);`	`);`
`else	`else
`assign pri8_out = 0;`	`assign pri8_out = 0;`
`endif	`endif

`ifdef HAVE_CH9	`ifdef WDMA_HAVE_CH9
`wb_dma_pri_enc_sub u9(`	`wb_dma_pri_enc_sub u9(`
`.valid( valid[9] ),`	`.valid( valid[9] ),`
`.pri_in( pri9 ),`	`.pri_in( pri9 ),`
`.pri_out( pri9_out )`	`.pri_out( pri9_out )`
`);`	`);`
`else	`else
`assign pri9_out = 0;`	`assign pri9_out = 0;`
`endif	`endif

`ifdef HAVE_CH10	`ifdef WDMA_HAVE_CH10
`wb_dma_pri_enc_sub u10(`	`wb_dma_pri_enc_sub u10(`
`.valid( valid[10] ),`	`.valid( valid[10] ),`
`.pri_in( pri10 ),`	`.pri_in( pri10 ),`
`.pri_out( pri10_out )`	`.pri_out( pri10_out )`
`);`	`);`
`else	`else
`assign pri10_out = 0;`	`assign pri10_out = 0;`
`endif	`endif

`ifdef HAVE_CH11	`ifdef WDMA_HAVE_CH11
`wb_dma_pri_enc_sub u11(`	`wb_dma_pri_enc_sub u11(`
`.valid( valid[11] ),`	`.valid( valid[11] ),`
`.pri_in( pri11 ),`	`.pri_in( pri11 ),`
`.pri_out( pri11_out )`	`.pri_out( pri11_out )`
`);`	`);`
`else	`else
`assign pri11_out = 0;`	`assign pri11_out = 0;`
`endif	`endif

`ifdef HAVE_CH12	`ifdef WDMA_HAVE_CH12
`wb_dma_pri_enc_sub u12(`	`wb_dma_pri_enc_sub u12(`
`.valid( valid[12] ),`	`.valid( valid[12] ),`
`.pri_in( pri12 ),`	`.pri_in( pri12 ),`
`.pri_out( pri12_out )`	`.pri_out( pri12_out )`
`);`	`);`
`else	`else
`assign pri12_out = 0;`	`assign pri12_out = 0;`
`endif	`endif

`ifdef HAVE_CH13	`ifdef WDMA_HAVE_CH13
`wb_dma_pri_enc_sub u13(`	`wb_dma_pri_enc_sub u13(`
`.valid( valid[13] ),`	`.valid( valid[13] ),`
`.pri_in( pri13 ),`	`.pri_in( pri13 ),`
`.pri_out( pri13_out )`	`.pri_out( pri13_out )`
`);`	`);`
`else	`else
`assign pri13_out = 0;`	`assign pri13_out = 0;`
`endif	`endif

`ifdef HAVE_CH14	`ifdef WDMA_HAVE_CH14
`wb_dma_pri_enc_sub u14(`	`wb_dma_pri_enc_sub u14(`
`.valid( valid[14] ),`	`.valid( valid[14] ),`
`.pri_in( pri14 ),`	`.pri_in( pri14 ),`
`.pri_out( pri14_out )`	`.pri_out( pri14_out )`
`);`	`);`
`else	`else
`assign pri14_out = 0;`	`assign pri14_out = 0;`
`endif	`endif

`ifdef HAVE_CH15	`ifdef WDMA_HAVE_CH15
`wb_dma_pri_enc_sub u15(`	`wb_dma_pri_enc_sub u15(`
`.valid( valid[15] ),`	`.valid( valid[15] ),`
`.pri_in( pri15 ),`	`.pri_in( pri15 ),`
`.pri_out( pri15_out )`	`.pri_out( pri15_out )`
`);`	`);`
`else	`else
`assign pri15_out = 0;`	`assign pri15_out = 0;`
`endif	`endif

`ifdef HAVE_CH16	`ifdef WDMA_HAVE_CH16
`wb_dma_pri_enc_sub u16(`	`wb_dma_pri_enc_sub u16(`
`.valid( valid[16] ),`	`.valid( valid[16] ),`
`.pri_in( pri16 ),`	`.pri_in( pri16 ),`
`.pri_out( pri16_out )`	`.pri_out( pri16_out )`
`);`	`);`
`else	`else
`assign pri16_out = 0;`	`assign pri16_out = 0;`
`endif	`endif

`ifdef HAVE_CH17	`ifdef WDMA_HAVE_CH17
`wb_dma_pri_enc_sub u17(`	`wb_dma_pri_enc_sub u17(`
`.valid( valid[17] ),`	`.valid( valid[17] ),`
`.pri_in( pri17 ),`	`.pri_in( pri17 ),`
`.pri_out( pri17_out )`	`.pri_out( pri17_out )`
`);`	`);`
`else	`else
`assign pri17_out = 0;`	`assign pri17_out = 0;`
`endif	`endif

`ifdef HAVE_CH18	`ifdef WDMA_HAVE_CH18
`wb_dma_pri_enc_sub u18(`	`wb_dma_pri_enc_sub u18(`
`.valid( valid[18] ),`	`.valid( valid[18] ),`
`.pri_in( pri18 ),`	`.pri_in( pri18 ),`
`.pri_out( pri18_out )`	`.pri_out( pri18_out )`
`);`	`);`
`else	`else
`assign pri18_out = 0;`	`assign pri18_out = 0;`
`endif	`endif

`ifdef HAVE_CH19	`ifdef WDMA_HAVE_CH19
`wb_dma_pri_enc_sub u19(`	`wb_dma_pri_enc_sub u19(`
`.valid( valid[19] ),`	`.valid( valid[19] ),`
`.pri_in( pri19 ),`	`.pri_in( pri19 ),`
`.pri_out( pri19_out )`	`.pri_out( pri19_out )`
`);`	`);`
`else	`else
`assign pri19_out = 0;`	`assign pri19_out = 0;`
`endif	`endif

`ifdef HAVE_CH20	`ifdef WDMA_HAVE_CH20
`wb_dma_pri_enc_sub u20(`	`wb_dma_pri_enc_sub u20(`
`.valid( valid[20] ),`	`.valid( valid[20] ),`
`.pri_in( pri20 ),`	`.pri_in( pri20 ),`
`.pri_out( pri20_out )`	`.pri_out( pri20_out )`
`);`	`);`
`else	`else
`assign pri20_out = 0;`	`assign pri20_out = 0;`
`endif	`endif

`ifdef HAVE_CH21	`ifdef WDMA_HAVE_CH21
`wb_dma_pri_enc_sub u21(`	`wb_dma_pri_enc_sub u21(`
`.valid( valid[21] ),`	`.valid( valid[21] ),`
`.pri_in( pri21 ),`	`.pri_in( pri21 ),`
`.pri_out( pri21_out )`	`.pri_out( pri21_out )`
`);`	`);`
`else	`else
`assign pri21_out = 0;`	`assign pri21_out = 0;`
`endif	`endif

`ifdef HAVE_CH22	`ifdef WDMA_HAVE_CH22
`wb_dma_pri_enc_sub u22(`	`wb_dma_pri_enc_sub u22(`
`.valid( valid[22] ),`	`.valid( valid[22] ),`
`.pri_in( pri22 ),`	`.pri_in( pri22 ),`
`.pri_out( pri22_out )`	`.pri_out( pri22_out )`
`);`	`);`
`else	`else
`assign pri22_out = 0;`	`assign pri22_out = 0;`
`endif	`endif

`ifdef HAVE_CH23	`ifdef WDMA_HAVE_CH23
`wb_dma_pri_enc_sub u23(`	`wb_dma_pri_enc_sub u23(`
`.valid( valid[23] ),`	`.valid( valid[23] ),`
`.pri_in( pri23 ),`	`.pri_in( pri23 ),`
`.pri_out( pri23_out )`	`.pri_out( pri23_out )`
`);`	`);`
`else	`else
`assign pri23_out = 0;`	`assign pri23_out = 0;`
`endif	`endif

`ifdef HAVE_CH24	`ifdef WDMA_HAVE_CH24
`wb_dma_pri_enc_sub u24(`	`wb_dma_pri_enc_sub u24(`
`.valid( valid[24] ),`	`.valid( valid[24] ),`
`.pri_in( pri24 ),`	`.pri_in( pri24 ),`
`.pri_out( pri24_out )`	`.pri_out( pri24_out )`
`);`	`);`
`else	`else
`assign pri24_out = 0;`	`assign pri24_out = 0;`
`endif	`endif

`ifdef HAVE_CH25	`ifdef WDMA_HAVE_CH25
`wb_dma_pri_enc_sub u25(`	`wb_dma_pri_enc_sub u25(`
`.valid( valid[25] ),`	`.valid( valid[25] ),`
`.pri_in( pri25 ),`	`.pri_in( pri25 ),`
`.pri_out( pri25_out )`	`.pri_out( pri25_out )`
`);`	`);`
`else	`else
`assign pri25_out = 0;`	`assign pri25_out = 0;`
`endif	`endif

`ifdef HAVE_CH26	`ifdef WDMA_HAVE_CH26
`wb_dma_pri_enc_sub u26(`	`wb_dma_pri_enc_sub u26(`
`.valid( valid[26] ),`	`.valid( valid[26] ),`
`.pri_in( pri26 ),`	`.pri_in( pri26 ),`
`.pri_out( pri26_out )`	`.pri_out( pri26_out )`
`);`	`);`
`else	`else
`assign pri26_out = 0;`	`assign pri26_out = 0;`
`endif	`endif

`ifdef HAVE_CH27	`ifdef WDMA_HAVE_CH27
`wb_dma_pri_enc_sub u27(`	`wb_dma_pri_enc_sub u27(`
`.valid( valid[27] ),`	`.valid( valid[27] ),`
`.pri_in( pri27 ),`	`.pri_in( pri27 ),`
`.pri_out( pri27_out )`	`.pri_out( pri27_out )`
`);`	`);`
`else	`else
`assign pri27_out = 0;`	`assign pri27_out = 0;`
`endif	`endif

`ifdef HAVE_CH28	`ifdef WDMA_HAVE_CH28
`wb_dma_pri_enc_sub u28(`	`wb_dma_pri_enc_sub u28(`
`.valid( valid[28] ),`	`.valid( valid[28] ),`
`.pri_in( pri28 ),`	`.pri_in( pri28 ),`
`.pri_out( pri28_out )`	`.pri_out( pri28_out )`
`);`	`);`
`else	`else
`assign pri28_out = 0;`	`assign pri28_out = 0;`
`endif	`endif

`ifdef HAVE_CH29	`ifdef WDMA_HAVE_CH29
`wb_dma_pri_enc_sub u29(`	`wb_dma_pri_enc_sub u29(`
`.valid( valid[29] ),`	`.valid( valid[29] ),`
`.pri_in( pri29 ),`	`.pri_in( pri29 ),`
`.pri_out( pri29_out )`	`.pri_out( pri29_out )`
`);`	`);`
`else	`else
`assign pri29_out = 0;`	`assign pri29_out = 0;`
`endif	`endif

`ifdef HAVE_CH30	`ifdef WDMA_HAVE_CH30
`wb_dma_pri_enc_sub u30(`	`wb_dma_pri_enc_sub u30(`
`.valid( valid[30] ),`	`.valid( valid[30] ),`
`.pri_in( pri30 ),`	`.pri_in( pri30 ),`
`.pri_out( pri30_out )`	`.pri_out( pri30_out )`
`);`	`);`
Line 425...	Line 430...
`pri20_out \| pri21_out \| pri22_out \| pri23_out \|`	`pri20_out \| pri21_out \| pri22_out \| pri23_out \|`
`pri24_out \| pri25_out \| pri26_out \| pri27_out \|`	`pri24_out \| pri25_out \| pri26_out \| pri27_out \|`
`pri28_out \| pri29_out \| pri30_out;`	`pri28_out \| pri29_out \| pri30_out;`

`always @(posedge clk)`	`always @(posedge clk)`
`ifdef PRI_8	`ifdef WDMA_PRI_8
`if(pri_out_tmp[7]) pri_out <= #1 3'h7;`	`if(pri_out_tmp[7]) pri_out <= #1 3'h7;`
`else`	`else`
`if(pri_out_tmp[6]) pri_out <= #1 3'h6;`	`if(pri_out_tmp[6]) pri_out <= #1 3'h6;`
`else`	`else`
`if(pri_out_tmp[5]) pri_out <= #1 3'h5;`	`if(pri_out_tmp[5]) pri_out <= #1 3'h5;`
Line 439...	Line 444...
`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`	`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`
`else`	`else`
`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`	`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`
`else`	`else`
`endif	`endif
`ifdef PRI_4	`ifdef WDMA_PRI_4
`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`	`if(pri_out_tmp[3]) pri_out <= #1 3'h3;`
`else`	`else`
`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`	`if(pri_out_tmp[2]) pri_out <= #1 3'h2;`
`else`	`else`
`endif	`endif

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: wb_dma_ch_pri_enc.v,v 1.2 2001-08-07 08:00:43 rudi Exp $

//  $Id: wb_dma_ch_pri_enc.v,v 1.3 2001-08-15 05:40:30 rudi Exp $

//

//

//  $Date: 2001-08-07 08:00:43 $

//  $Date: 2001-08-15 05:40:30 $

//  $Revision: 1.2 $

//  $Revision: 1.3 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.2  2001/08/07 08:00:43  rudi

//

//

//               Split up priority encoder modules to separate files

//

//               Revision 1.1  2001/07/29 08:57:02  rudi

//               Revision 1.1  2001/07/29 08:57:02  rudi

//

//

//

//

//               1) Changed Directory Structure

//               1) Changed Directory Structure

//               2) Added restart signal (REST)

//               2) Added restart signal (REST)

Line 108...

Line 113...

wire    [7:0]    pri28_out, pri29_out, pri30_out;

wire    [7:0]    pri28_out, pri29_out, pri30_out;

wire    [7:0]    pri_out_tmp;

wire    [7:0]    pri_out_tmp;

reg     [2:0]    pri_out;

reg     [2:0]    pri_out;

`ifdef HAVE_CH1

`ifdef WDMA_HAVE_CH1

wb_dma_pri_enc_sub u0(

wb_dma_pri_enc_sub u0(

                .valid(         valid[0] ),

                .valid(         valid[0] ),

                .pri_in(        pri0            ),

                .pri_in(        pri0            ),

                .pri_out(       pri0_out        )

                .pri_out(       pri0_out        )

);

);

Line 125...

Line 130...

`else

`else

assign pri0_out = 0;

assign pri0_out = 0;

assign pri1_out = 0;

assign pri1_out = 0;

`endif

`endif

`ifdef HAVE_CH2

`ifdef WDMA_HAVE_CH2

wb_dma_pri_enc_sub u2(

wb_dma_pri_enc_sub u2(

                .valid(         valid[2]        ),

                .valid(         valid[2]        ),

                .pri_in(        pri2            ),

                .pri_in(        pri2            ),

                .pri_out(       pri2_out        )

                .pri_out(       pri2_out        )

);

);

`else

`else

assign pri2_out = 0;

assign pri2_out = 0;

`endif

`endif

`ifdef HAVE_CH3

`ifdef WDMA_HAVE_CH3

wb_dma_pri_enc_sub u3(

wb_dma_pri_enc_sub u3(

                .valid(         valid[3]        ),

                .valid(         valid[3]        ),

                .pri_in(        pri3            ),

                .pri_in(        pri3            ),

                .pri_out(       pri3_out        )

                .pri_out(       pri3_out        )

);

);

`else

`else

assign pri3_out = 0;

assign pri3_out = 0;

`endif

`endif

`ifdef HAVE_CH4

`ifdef WDMA_HAVE_CH4

wb_dma_pri_enc_sub u4(

wb_dma_pri_enc_sub u4(

                .valid(         valid[4]        ),

                .valid(         valid[4]        ),

                .pri_in(        pri4            ),

                .pri_in(        pri4            ),

                .pri_out(       pri4_out        )

                .pri_out(       pri4_out        )

);

);

`else

`else

assign pri4_out = 0;

assign pri4_out = 0;

`endif

`endif

`ifdef HAVE_CH5

`ifdef WDMA_HAVE_CH5

wb_dma_pri_enc_sub u5(

wb_dma_pri_enc_sub u5(

                .valid(         valid[5]        ),

                .valid(         valid[5]        ),

                .pri_in(        pri5            ),

                .pri_in(        pri5            ),

                .pri_out(       pri5_out        )

                .pri_out(       pri5_out        )

);

);

`else

`else

assign pri5_out = 0;

assign pri5_out = 0;

`endif

`endif

`ifdef HAVE_CH6

`ifdef WDMA_HAVE_CH6

wb_dma_pri_enc_sub u6(

wb_dma_pri_enc_sub u6(

                .valid(         valid[6]        ),

                .valid(         valid[6]        ),

                .pri_in(        pri6            ),

                .pri_in(        pri6            ),

                .pri_out(       pri6_out        )

                .pri_out(       pri6_out        )

);

);

`else

`else

assign pri6_out = 0;

assign pri6_out = 0;

`endif

`endif

`ifdef HAVE_CH7

`ifdef WDMA_HAVE_CH7

wb_dma_pri_enc_sub u7(

wb_dma_pri_enc_sub u7(

                .valid(         valid[7]        ),

                .valid(         valid[7]        ),

                .pri_in(        pri7            ),

                .pri_in(        pri7            ),

                .pri_out(       pri7_out        )

                .pri_out(       pri7_out        )

);

);

`else

`else

assign pri7_out = 0;

assign pri7_out = 0;

`endif

`endif

`ifdef HAVE_CH8

`ifdef WDMA_HAVE_CH8

wb_dma_pri_enc_sub u8(

wb_dma_pri_enc_sub u8(

                .valid(         valid[8]        ),

                .valid(         valid[8]        ),

                .pri_in(        pri8            ),

                .pri_in(        pri8            ),

                .pri_out(       pri8_out        )

                .pri_out(       pri8_out        )

);

);

`else

`else

assign pri8_out = 0;

assign pri8_out = 0;

`endif

`endif

`ifdef HAVE_CH9

`ifdef WDMA_HAVE_CH9

wb_dma_pri_enc_sub u9(

wb_dma_pri_enc_sub u9(

                .valid(         valid[9]        ),

                .valid(         valid[9]        ),

                .pri_in(        pri9            ),

                .pri_in(        pri9            ),

                .pri_out(       pri9_out        )

                .pri_out(       pri9_out        )

);

);

`else

`else

assign pri9_out = 0;

assign pri9_out = 0;

`endif

`endif

`ifdef HAVE_CH10

`ifdef WDMA_HAVE_CH10

wb_dma_pri_enc_sub u10(

wb_dma_pri_enc_sub u10(

                .valid(         valid[10]       ),

                .valid(         valid[10]       ),

                .pri_in(        pri10           ),

                .pri_in(        pri10           ),

                .pri_out(       pri10_out       )

                .pri_out(       pri10_out       )

);

);

`else

`else

assign pri10_out = 0;

assign pri10_out = 0;

`endif

`endif

`ifdef HAVE_CH11

`ifdef WDMA_HAVE_CH11

wb_dma_pri_enc_sub u11(

wb_dma_pri_enc_sub u11(

                .valid(         valid[11]       ),

                .valid(         valid[11]       ),

                .pri_in(        pri11           ),

                .pri_in(        pri11           ),

                .pri_out(       pri11_out       )

                .pri_out(       pri11_out       )

);

);

`else

`else

assign pri11_out = 0;

assign pri11_out = 0;

`endif

`endif

`ifdef HAVE_CH12

`ifdef WDMA_HAVE_CH12

wb_dma_pri_enc_sub u12(

wb_dma_pri_enc_sub u12(

                .valid(         valid[12]       ),

                .valid(         valid[12]       ),

                .pri_in(        pri12           ),

                .pri_in(        pri12           ),

                .pri_out(       pri12_out       )

                .pri_out(       pri12_out       )

);

);

`else

`else

assign pri12_out = 0;

assign pri12_out = 0;

`endif

`endif

`ifdef HAVE_CH13

`ifdef WDMA_HAVE_CH13

wb_dma_pri_enc_sub u13(

wb_dma_pri_enc_sub u13(

                .valid(         valid[13]       ),

                .valid(         valid[13]       ),

                .pri_in(        pri13           ),

                .pri_in(        pri13           ),

                .pri_out(       pri13_out       )

                .pri_out(       pri13_out       )

);

);

`else

`else

assign pri13_out = 0;

assign pri13_out = 0;

`endif

`endif

`ifdef HAVE_CH14

`ifdef WDMA_HAVE_CH14

wb_dma_pri_enc_sub u14(

wb_dma_pri_enc_sub u14(

                .valid(         valid[14]       ),

                .valid(         valid[14]       ),

                .pri_in(        pri14           ),

                .pri_in(        pri14           ),

                .pri_out(       pri14_out       )

                .pri_out(       pri14_out       )

);

);

`else

`else

assign pri14_out = 0;

assign pri14_out = 0;

`endif

`endif

`ifdef HAVE_CH15

`ifdef WDMA_HAVE_CH15

wb_dma_pri_enc_sub u15(

wb_dma_pri_enc_sub u15(

                .valid(         valid[15]       ),

                .valid(         valid[15]       ),

                .pri_in(        pri15           ),

                .pri_in(        pri15           ),

                .pri_out(       pri15_out       )

                .pri_out(       pri15_out       )

);

);

`else

`else

assign pri15_out = 0;

assign pri15_out = 0;

`endif

`endif

`ifdef HAVE_CH16

`ifdef WDMA_HAVE_CH16

wb_dma_pri_enc_sub u16(

wb_dma_pri_enc_sub u16(

                .valid(         valid[16]       ),

                .valid(         valid[16]       ),

                .pri_in(        pri16           ),

                .pri_in(        pri16           ),

                .pri_out(       pri16_out       )

                .pri_out(       pri16_out       )

);

);

`else

`else

assign pri16_out = 0;

assign pri16_out = 0;

`endif

`endif

`ifdef HAVE_CH17

`ifdef WDMA_HAVE_CH17

wb_dma_pri_enc_sub u17(

wb_dma_pri_enc_sub u17(

                .valid(         valid[17]       ),

                .valid(         valid[17]       ),

                .pri_in(        pri17           ),

                .pri_in(        pri17           ),

                .pri_out(       pri17_out       )

                .pri_out(       pri17_out       )

);

);

`else

`else

assign pri17_out = 0;

assign pri17_out = 0;

`endif

`endif

`ifdef HAVE_CH18

`ifdef WDMA_HAVE_CH18

wb_dma_pri_enc_sub u18(

wb_dma_pri_enc_sub u18(

                .valid(         valid[18]       ),

                .valid(         valid[18]       ),

                .pri_in(        pri18           ),

                .pri_in(        pri18           ),

                .pri_out(       pri18_out       )

                .pri_out(       pri18_out       )

);

);

`else

`else

assign pri18_out = 0;

assign pri18_out = 0;

`endif

`endif

`ifdef HAVE_CH19

`ifdef WDMA_HAVE_CH19

wb_dma_pri_enc_sub u19(

wb_dma_pri_enc_sub u19(

                .valid(         valid[19]       ),

                .valid(         valid[19]       ),

                .pri_in(        pri19           ),

                .pri_in(        pri19           ),

                .pri_out(       pri19_out       )

                .pri_out(       pri19_out       )

);

);

`else

`else

assign pri19_out = 0;

assign pri19_out = 0;

`endif

`endif

`ifdef HAVE_CH20

`ifdef WDMA_HAVE_CH20

wb_dma_pri_enc_sub u20(

wb_dma_pri_enc_sub u20(

                .valid(         valid[20]       ),

                .valid(         valid[20]       ),

                .pri_in(        pri20           ),

                .pri_in(        pri20           ),

                .pri_out(       pri20_out       )

                .pri_out(       pri20_out       )

);

);

`else

`else

assign pri20_out = 0;

assign pri20_out = 0;

`endif

`endif

`ifdef HAVE_CH21

`ifdef WDMA_HAVE_CH21

wb_dma_pri_enc_sub u21(

wb_dma_pri_enc_sub u21(

                .valid(         valid[21]       ),

                .valid(         valid[21]       ),

                .pri_in(        pri21           ),

                .pri_in(        pri21           ),

                .pri_out(       pri21_out       )

                .pri_out(       pri21_out       )

);

);

`else

`else

assign pri21_out = 0;

assign pri21_out = 0;

`endif

`endif

`ifdef HAVE_CH22

`ifdef WDMA_HAVE_CH22

wb_dma_pri_enc_sub u22(

wb_dma_pri_enc_sub u22(

                .valid(         valid[22]       ),

                .valid(         valid[22]       ),

                .pri_in(        pri22           ),

                .pri_in(        pri22           ),

                .pri_out(       pri22_out       )

                .pri_out(       pri22_out       )

);

);

`else

`else

assign pri22_out = 0;

assign pri22_out = 0;

`endif

`endif

`ifdef HAVE_CH23

`ifdef WDMA_HAVE_CH23

wb_dma_pri_enc_sub u23(

wb_dma_pri_enc_sub u23(

                .valid(         valid[23]       ),

                .valid(         valid[23]       ),

                .pri_in(        pri23           ),

                .pri_in(        pri23           ),

                .pri_out(       pri23_out       )

                .pri_out(       pri23_out       )

);

);

`else

`else

assign pri23_out = 0;

assign pri23_out = 0;

`endif

`endif

`ifdef HAVE_CH24

`ifdef WDMA_HAVE_CH24

wb_dma_pri_enc_sub u24(

wb_dma_pri_enc_sub u24(

                .valid(         valid[24]       ),

                .valid(         valid[24]       ),

                .pri_in(        pri24           ),

                .pri_in(        pri24           ),

                .pri_out(       pri24_out       )

                .pri_out(       pri24_out       )

);

);

`else

`else

assign pri24_out = 0;

assign pri24_out = 0;

`endif

`endif

`ifdef HAVE_CH25

`ifdef WDMA_HAVE_CH25

wb_dma_pri_enc_sub u25(

wb_dma_pri_enc_sub u25(

                .valid(         valid[25]       ),

                .valid(         valid[25]       ),

                .pri_in(        pri25           ),

                .pri_in(        pri25           ),

                .pri_out(       pri25_out       )

                .pri_out(       pri25_out       )

);

);

`else

`else

assign pri25_out = 0;

assign pri25_out = 0;

`endif

`endif

`ifdef HAVE_CH26

`ifdef WDMA_HAVE_CH26

wb_dma_pri_enc_sub u26(

wb_dma_pri_enc_sub u26(

                .valid(         valid[26]       ),

                .valid(         valid[26]       ),

                .pri_in(        pri26           ),

                .pri_in(        pri26           ),

                .pri_out(       pri26_out       )

                .pri_out(       pri26_out       )

);

);

`else

`else

assign pri26_out = 0;

assign pri26_out = 0;

`endif

`endif

`ifdef HAVE_CH27

`ifdef WDMA_HAVE_CH27

wb_dma_pri_enc_sub u27(

wb_dma_pri_enc_sub u27(

                .valid(         valid[27]       ),

                .valid(         valid[27]       ),

                .pri_in(        pri27           ),

                .pri_in(        pri27           ),

                .pri_out(       pri27_out       )

                .pri_out(       pri27_out       )

);

);

`else

`else

assign pri27_out = 0;

assign pri27_out = 0;

`endif

`endif

`ifdef HAVE_CH28

`ifdef WDMA_HAVE_CH28

wb_dma_pri_enc_sub u28(

wb_dma_pri_enc_sub u28(

                .valid(         valid[28]       ),

                .valid(         valid[28]       ),

                .pri_in(        pri28           ),

                .pri_in(        pri28           ),

                .pri_out(       pri28_out       )

                .pri_out(       pri28_out       )

);

);

`else

`else

assign pri28_out = 0;

assign pri28_out = 0;

`endif

`endif

`ifdef HAVE_CH29

`ifdef WDMA_HAVE_CH29

wb_dma_pri_enc_sub u29(

wb_dma_pri_enc_sub u29(

                .valid(         valid[29]       ),

                .valid(         valid[29]       ),

                .pri_in(        pri29           ),

                .pri_in(        pri29           ),

                .pri_out(       pri29_out       )

                .pri_out(       pri29_out       )

);

);

`else

`else

assign pri29_out = 0;

assign pri29_out = 0;

`endif

`endif

`ifdef HAVE_CH30

`ifdef WDMA_HAVE_CH30

wb_dma_pri_enc_sub u30(

wb_dma_pri_enc_sub u30(

                .valid(         valid[30]       ),

                .valid(         valid[30]       ),

                .pri_in(        pri30           ),

                .pri_in(        pri30           ),

                .pri_out(       pri30_out       )

                .pri_out(       pri30_out       )

);

);

Line 425...

Line 430...

                        pri20_out | pri21_out | pri22_out | pri23_out |

                        pri20_out | pri21_out | pri22_out | pri23_out |

                        pri24_out | pri25_out | pri26_out | pri27_out |

                        pri24_out | pri25_out | pri26_out | pri27_out |

                        pri28_out | pri29_out | pri30_out;

                        pri28_out | pri29_out | pri30_out;

always @(posedge clk)

always @(posedge clk)

`ifdef PRI_8

`ifdef WDMA_PRI_8

        if(pri_out_tmp[7])      pri_out <= #1 3'h7;

        if(pri_out_tmp[7])      pri_out <= #1 3'h7;

        else

        else

        if(pri_out_tmp[6])      pri_out <= #1 3'h6;

        if(pri_out_tmp[6])      pri_out <= #1 3'h6;

        else

        else

        if(pri_out_tmp[5])      pri_out <= #1 3'h5;

        if(pri_out_tmp[5])      pri_out <= #1 3'h5;

Line 439...

Line 444...

        if(pri_out_tmp[3])      pri_out <= #1 3'h3;

        if(pri_out_tmp[3])      pri_out <= #1 3'h3;

        else

        else

        if(pri_out_tmp[2])      pri_out <= #1 3'h2;

        if(pri_out_tmp[2])      pri_out <= #1 3'h2;

        else

        else

`endif

`endif

`ifdef PRI_4

`ifdef WDMA_PRI_4

        if(pri_out_tmp[3])      pri_out <= #1 3'h3;

        if(pri_out_tmp[3])      pri_out <= #1 3'h3;

        else

        else

        if(pri_out_tmp[2])      pri_out <= #1 3'h2;

        if(pri_out_tmp[2])      pri_out <= #1 3'h2;

        else

        else

`endif

`endif

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_ch_pri_enc.v] - Diff between revs 6 and 8