| Line 35... |
Line 35... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_ch_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
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// $Id: wb_dma_ch_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $
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//
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//
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// $Date: 2001-08-15 05:40:30 $
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// $Date: 2001-10-19 04:35:04 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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// 2) Added restart signal (REST)
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| Line 92... |
Line 98... |
ptr_set
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ptr_set
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);
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);
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parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID
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parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID
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parameter [0:0] CH_EN = 1'b1; // This channel exists
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parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS
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parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS
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parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors
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parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors
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parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers
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parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers
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input clk, rst;
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input clk, rst;
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| Line 191... |
Line 198... |
////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Aliases
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// Aliases
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//
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//
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assign ch_adr0 = {ch_adr0_r, 2'h0};
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assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;
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assign ch_adr1 = {ch_adr1_r, 2'h0};
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assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;
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assign ch_am0 = {ch_am0_r, 4'h0};
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assign ch_am0 = CH_EN ? {ch_am0_r, 4'h0} : 32'h0;
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assign ch_am1 = {ch_am1_r, 4'h0};
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assign ch_am1 = CH_EN ? {ch_am1_r, 4'h0} : 32'h0;
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assign sw_pointer = {sw_pointer_r,2'h0};
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assign sw_pointer = CH_EN ? {sw_pointer_r,2'h0} : 32'h0;
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assign pointer = {pointer_r, 3'h0, ptr_valid};
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assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
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assign pointer_s = {pointer_sr, 4'h0};
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assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
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assign ch_csr = {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable};
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
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assign ch_txsz = {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r};
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assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;
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assign ch_enable = ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1);
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assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// CH0 control signals
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// CH0 control signals
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//
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//
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parameter [4:0] CH_ADR = CH_NO + 5'h1;
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parameter [4:0] CH_ADR = CH_NO + 5'h1;
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assign ch_csr_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_csr_re = wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_txsz_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
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assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
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assign ch_adr0_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
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assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
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assign ch_am0_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
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assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
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assign ch_adr1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
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assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
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assign ch_am1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
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assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
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assign pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
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assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
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assign sw_pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
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assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
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assign ch_done_we = (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
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assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
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(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
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(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
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assign chunk_done_we = (ch_sel==CH_NO) & dma_done;
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assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;
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assign ch_err_we = (ch_sel==CH_NO) & dma_err;
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assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;
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assign ch_csr_dewe = de_csr_we & (ch_sel==CH_NO);
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assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);
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assign ch_txsz_dewe = de_txsz_we & (ch_sel==CH_NO);
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assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);
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assign ch_adr0_dewe = de_adr0_we & (ch_sel==CH_NO);
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assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);
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assign ch_adr1_dewe = de_adr1_we & (ch_sel==CH_NO);
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assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);
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assign ptr_inv = ((ch_sel==CH_NO) & dma_done_all) | ndnr;
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assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
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assign this_ptr_set = ptr_set & (ch_sel==CH_NO);
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assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);
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always @(posedge clk)
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always @(posedge clk)
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ch_rl <= #1 HAVE_ARS & (
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ch_rl <= #1 CH_EN & HAVE_ARS & (
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(rest_en & dma_rest) |
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(rest_en & dma_rest) |
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((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
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((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
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);
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);
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// ---------------------------------------------------
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// ---------------------------------------------------
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// Pointers
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// Pointers
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ptr_valid <= #1 1'b0;
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if(!rst) ptr_valid <= #1 1'b0;
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else
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else
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if(HAVE_ED)
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if(CH_EN & HAVE_ED)
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begin
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begin
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if( this_ptr_set | (rest_en & dma_rest) )
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if( this_ptr_set | (rest_en & dma_rest) )
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ptr_valid <= #1 1'b1;
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ptr_valid <= #1 1'b1;
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else
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else
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if(ptr_inv) ptr_valid <= #1 1'b0;
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if(ptr_inv) ptr_valid <= #1 1'b0;
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| Line 258... |
Line 265... |
else ptr_valid <= #1 1'b0;
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else ptr_valid <= #1 1'b0;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_eol <= #1 1'b0;
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if(!rst) ch_eol <= #1 1'b0;
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else
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else
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if(HAVE_ED)
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if(CH_EN & HAVE_ED)
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begin
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begin
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if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
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if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
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else
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else
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if(ch_done_we) ch_eol <= #1 1'b0;
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if(ch_done_we) ch_eol <= #1 1'b0;
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end
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end
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else ch_eol <= #1 1'b0;
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else ch_eol <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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if(HAVE_ED)
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if(CH_EN & HAVE_ED)
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begin
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begin
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if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];
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if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];
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else
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else
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if(this_ptr_set) pointer_r <= #1 de_csr[31:4];
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if(this_ptr_set) pointer_r <= #1 de_csr[31:4];
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end
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end
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else pointer_r <= #1 1'b0;
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else pointer_r <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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if(HAVE_ED)
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if(CH_EN & HAVE_ED)
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begin
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begin
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if(this_ptr_set) pointer_sr <= #1 pointer_r;
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if(this_ptr_set) pointer_sr <= #1 pointer_r;
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end
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end
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else pointer_sr <= #1 1'b0;
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else pointer_sr <= #1 1'b0;
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| Line 288... |
Line 295... |
// CSR
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// CSR
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_csr_r <= #1 1'b0;
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if(!rst) ch_csr_r <= #1 1'b0;
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else
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else
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if(CH_EN)
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begin
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if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
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if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
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else
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else
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begin
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begin
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if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
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if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
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if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
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if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
|
end
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end
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end
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// done bit
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// done bit
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_done <= #1 1'b0;
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if(!rst) ch_done <= #1 1'b0;
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else
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else
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if(CH_EN)
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begin
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if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
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if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
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else
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else
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if(ch_done_we) ch_done <= #1 1'b1;
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if(ch_done_we) ch_done <= #1 1'b1;
|
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end
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// busy bit
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// busy bit
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always @(posedge clk)
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always @(posedge clk)
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ch_busy <= #1 (ch_sel==CH_NO) & dma_busy;
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ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
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|
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// stop bit
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// stop bit
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always @(posedge clk)
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always @(posedge clk)
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ch_stop <= #1 ch_csr_we & wb_rf_din[`WDMA_STOP];
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ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
|
|
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// error bit
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// error bit
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always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
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if(!rst) ch_err <= #1 1'b0;
|
if(!rst) ch_err <= #1 1'b0;
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else
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else
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if(CH_EN)
|
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begin
|
if(ch_err_we) ch_err <= #1 1'b1;
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if(ch_err_we) ch_err <= #1 1'b1;
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else
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else
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if(ch_csr_re) ch_err <= #1 1'b0;
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if(ch_csr_re) ch_err <= #1 1'b0;
|
|
end
|
|
|
// Priority Bits
|
// Priority Bits
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) ch_csr_r2 <= #1 3'h0;
|
if(!rst) ch_csr_r2 <= #1 3'h0;
|
else
|
else
|
if(ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];
|
if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];
|
|
|
// Restart Enable Bit (REST)
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// Restart Enable Bit (REST)
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always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
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if(!rst) rest_en <= #1 1'b0;
|
if(!rst) rest_en <= #1 1'b0;
|
else
|
else
|
if(ch_csr_we) rest_en <= #1 wb_rf_din[16];
|
if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];
|
|
|
// INT Mask
|
// INT Mask
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) ch_csr_r3 <= #1 3'h0;
|
if(!rst) ch_csr_r3 <= #1 3'h0;
|
else
|
else
|
if(ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];
|
if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];
|
|
|
// INT Source
|
// INT Source
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) int_src_r[2] <= #1 1'b0;
|
if(!rst) int_src_r[2] <= #1 1'b0;
|
else
|
else
|
|
if(CH_EN)
|
|
begin
|
if(chunk_done_we) int_src_r[2] <= #1 1'b1;
|
if(chunk_done_we) int_src_r[2] <= #1 1'b1;
|
else
|
else
|
if(ch_csr_re) int_src_r[2] <= #1 1'b0;
|
if(ch_csr_re) int_src_r[2] <= #1 1'b0;
|
|
end
|
|
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) int_src_r[1] <= #1 1'b0;
|
if(!rst) int_src_r[1] <= #1 1'b0;
|
else
|
else
|
|
if(CH_EN)
|
|
begin
|
if(ch_done_we) int_src_r[1] <= #1 1'b1;
|
if(ch_done_we) int_src_r[1] <= #1 1'b1;
|
else
|
else
|
if(ch_csr_re) int_src_r[1] <= #1 1'b0;
|
if(ch_csr_re) int_src_r[1] <= #1 1'b0;
|
|
end
|
|
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) int_src_r[0] <= #1 1'b0;
|
if(!rst) int_src_r[0] <= #1 1'b0;
|
else
|
else
|
|
if(CH_EN)
|
|
begin
|
if(ch_err_we) int_src_r[0] <= #1 1'b1;
|
if(ch_err_we) int_src_r[0] <= #1 1'b1;
|
else
|
else
|
if(ch_csr_re) int_src_r[0] <= #1 1'b0;
|
if(ch_csr_re) int_src_r[0] <= #1 1'b0;
|
|
end
|
|
|
// Interrupt Output
|
// Interrupt Output
|
assign int = |(int_src_r & ch_csr_r3);
|
assign int = |(int_src_r & ch_csr_r3);
|
|
|
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// TXZS
|
// TXZS
|
always @(posedge clk)
|
always @(posedge clk)
|
|
if(CH_EN)
|
|
begin
|
if(ch_txsz_we)
|
if(ch_txsz_we)
|
{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
|
{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
|
else
|
else
|
if(ch_txsz_dewe)
|
if(ch_txsz_dewe)
|
ch_tot_sz_r <= #1 de_txsz;
|
ch_tot_sz_r <= #1 de_txsz;
|
else
|
else
|
if(ch_rl)
|
if(ch_rl)
|
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
|
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
|
|
end
|
|
|
// txsz shadow register
|
// txsz shadow register
|
always @(posedge clk)
|
always @(posedge clk)
|
if(HAVE_ARS)
|
if(CH_EN & HAVE_ARS)
|
begin
|
begin
|
|
|
if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
|
if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
|
else
|
else
|
if(rest_en & ch_txsz_dewe & de_fetch_descr)
|
if(rest_en & ch_txsz_dewe & de_fetch_descr)
|
ch_txsz_s[11:0] <= #1 de_txsz[11:0];
|
ch_txsz_s[11:0] <= #1 de_txsz[11:0];
|
end
|
end
|
|
|
// Infinite Size indicator
|
// Infinite Size indicator
|
always @(posedge clk)
|
always @(posedge clk)
|
|
if(CH_EN)
|
|
begin
|
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
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if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
|
|
end
|
|
|
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// ADR0
|
// ADR0
|
always @(posedge clk)
|
always @(posedge clk)
|
|
if(CH_EN)
|
|
begin
|
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];
|
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];
|
else
|
else
|
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
|
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
|
else
|
else
|
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
|
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
|
|
end
|
|
|
// Adr0 shadow register
|
// Adr0 shadow register
|
always @(posedge clk)
|
always @(posedge clk)
|
if(HAVE_ARS)
|
if(CH_EN & HAVE_ARS)
|
begin
|
begin
|
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
|
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
|
else
|
else
|
if(rest_en & ch_adr0_dewe & de_fetch_descr)
|
if(rest_en & ch_adr0_dewe & de_fetch_descr)
|
ch_adr0_s <= #1 de_adr0[31:2];
|
ch_adr0_s <= #1 de_adr0[31:2];
|
| Line 418... |
Line 452... |
if(ch_am0_we & HAVE_CBUF) ch_am0_r <= #1 wb_rf_din[31:4];
|
if(ch_am0_we & HAVE_CBUF) ch_am0_r <= #1 wb_rf_din[31:4];
|
|
|
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// ADR1
|
// ADR1
|
always @(posedge clk)
|
always @(posedge clk)
|
|
if(CH_EN)
|
|
begin
|
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];
|
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];
|
else
|
else
|
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
|
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
|
else
|
else
|
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
|
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
|
|
end
|
|
|
// Adr1 shadow register
|
// Adr1 shadow register
|
always @(posedge clk)
|
always @(posedge clk)
|
if(HAVE_ARS)
|
if(CH_EN & HAVE_ARS)
|
begin
|
begin
|
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
|
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
|
else
|
else
|
if(rest_en & ch_adr1_dewe & de_fetch_descr)
|
if(rest_en & ch_adr1_dewe & de_fetch_descr)
|
ch_adr1_s <= #1 de_adr1[31:2];
|
ch_adr1_s <= #1 de_adr1[31:2];
|
| Line 439... |
Line 476... |
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// AM1
|
// AM1
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) ch_am1_r <= #1 28'hfffffff;
|
if(!rst) ch_am1_r <= #1 28'hfffffff;
|
else
|
else
|
if(ch_am1_we & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];
|
if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];
|
|
|
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// Software Pointer
|
// Software Pointer
|
always @(posedge clk or negedge rst)
|
always @(posedge clk or negedge rst)
|
if(!rst) sw_pointer_r <= #1 28'h0;
|
if(!rst) sw_pointer_r <= #1 28'h0;
|
else
|
else
|
if(sw_pointer_we & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];
|
if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];
|
|
|
// ---------------------------------------------------
|
// ---------------------------------------------------
|
// Software Pointer Match logic
|
// Software Pointer Match logic
|
|
|
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
|
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
ch_dis <= #1 HAVE_CBUF ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0;
|
ch_dis <= #1 (CH_EN & HAVE_CBUF) ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module wb_dma_ch_rf_dummy(clk, rst,
|
module wb_dma_ch_rf_dummy(clk, rst,
|
